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Moore’s Law is dead, long live Moore’s Law – part 3

Moore’s Law is dead, long live Moore’s Law – part 3
by Scotten Jones on 04-19-2015 at 4:00 am

In the second installment of this series we reviewed the cost drivers that have enabled the semiconductor industry to continue to cost reduce the cost per transistor year after year. In the next three installments we will discuss the product specific issues beginning with this installment discussing DRAM.

DRAM memory cell

DRAM memory is made up of a memory array and peripheral CMOS logic. The peripheral CMOS logic provides memory addressing, read amplifiers and other control functions. The peripheral logic is fabricated using relaxed line widths versus the memory array and it is the memory array that drives the technology of DRAMs.

The basic DRAM memory cell is the one transistor – one capacitor (1T1C) cell invented by Dennard of IBM. The basic cell is illustrated in figure 1.

Figure 1. DRAM 1T1C memory cell

In the 1T1C memory cell the memory value is stored on the capacitor, a charge indicates a one and no charge is a zero. In order for the cell to work properly the capacitor must be low leakage and have a minimum capacitance value of approximately 25fF. The access transistor controls access to the capacitor and traps the charge or lack of charge in place. The access transistor must be low leakage in order to retain the stored values.

The size of a DRAM memory cell is characterized as AF[SUP]2[/SUP] where F is the feature size and A is a factor determined by the architecture. Until around 2008 DRAM used folded bit line architecture because of its high noise immunity. Folded bit line architecture results in a DRAM memory cell 8F[SUP]2[/SUP] in size. Around 2008 open bit line architecture was adopted and although the noise immunity is not as good, open bit line architectures produce a 6F[SUP]2[/SUP] cell size with a migration path to a 4F[SUP]2[/SUP] cell.

DRAM Capacitor
The capacitance of a capacitor is given by the dielectric constant multiplied by the capacitor area divided by the dielectric thickness. To-date dielectric thicknesses have been scaled down to a value that is likely at or close to the minimum possible thickness. In order to minimize the horizontal area taken up by the capacitor a vertical structure has been adopted that is roughly 1.5 microns high. In order to maintain the mechanical integrity of these tall – incredibly narrow structures a nitride “MESH” has been added to the structure, some capacitors even incorporate two MESH layers. Figure 2. illustrates a current state of the art cylinder capacitor structure.

Figure 2. DRAM cylinder capacitor. Source, IC Knowledge

The height of capacitors is reaching practical limits for acceptable mechanical stability. The final opportunity to scale capacitors is to transition to dielectric films with higher dielectric constants. Early DRAM capacitors transitioned from silicon dioxide to nitride oxides to increase the dielectric constant (k) of the film. More recently higher K films such as hafnium and zirconium oxides have been used. The problem with these films is that as the k value of the film goes up (good), the band gap of the film goes down increasing leakage (bad). The solution to this has been to create nanolaminate films using high k hafnium oxide or zirconium oxide alternating with lower k aluminum oxide films to block leakage.

Currently a lot of work is being done on aluminum doped titanium oxide films (ATO) as the next generation dielectric. In order to maximize the k value of ATO films the film must be formed in a rutile phase. This is accomplished by the deposition of rutile phase ruthenium oxide as the bottom electrode and then depositing ATO on top of the ruthenium oxide. The ATO forms the same phase as the underlying ruthenium oxide. This is likely to result in a capacitor that can scale from the current 20nm generation two more generations to around 12nm.

Access transistor
At the same time that the capacitor needs to keep shrinking while maintaining a minimum capacitance with low leakage, the access transistor also has to shrink while maintaining low leakage. One key to low leakage in a MOS transistor is to maintain a long gate length. As we saw in the previous section on DRAM capacitors, the third dimension offers a way to minimize horizontal area while maintaining a required area or length. Figure 3. illustrates the recessed access transistor (RCAT) and spherical access transistor (SRCAT).

Figure 3. Recessed access transistor (RCAT) and spherical recessed access transistor (SRCAT)

The RCAT and SRCAT offer longer gate length by forceing the current flow down through the substrate adding a vertical component. RCAT and SRCAT entered use at 90nm and continued to be used down until the 3x nm generation of DRAMs.

At the 3x nm generation of DRAM the saddle fin was implemented. The fabrication and structure of a saddle fin is illustrated in figure 4.

Figure 4. Saddle fin fabrication and structure. Source, IC Knowledge

Eventually it is expected that a vertical cell access transistor (VCT) will be implemented allowing a 4F2 DRAM cell. Figure 5. Illustrates the VCT structure.

Figure 5. Vertical cell access transistor. Source, IC Knowledge

DRAM scaling
In the second installment in this series we presented the linewidth trend for Samsung’s DRAM. As DRAM have scaled down we have seen box capacitors give way to cylinder capacitors with higher and higher k films, and one and eventually two MESH layers. Access transistors have transitioned from planar transistor to RCAT/SRCAT and then saddle fins with VCT on the horizon. All of these transitions have increased the process complexity and cost. As linewidths have shrunk an increasing number of multipatterning layers has been required driving up mask counts. Figure 6. Illustrates the mask count trend for DRAM.

Figure 6. DRAM mask count trend. (assume EUV starting at 15nm)
Source, IC Knowledge Strategic Cost Model

Figure 7 illustrates the DRAM wafer cost trend.

Figure 7. DRAM wafer cost trend. Source, IC Knowledge Strategic Cost Model

Note that in Figure 7. there is no clear upward cost trend until 32nm where mask counts start to take off due to multipatterning.

Figure 8. illustrates the bit density trend for the memory array area.

Figure 8. DRAM bit density trend. Source, IC Knowledge Strategic Cost Model

Note that due to the range of bit density growth this figure is plotted on a log scale.

Figure 9. combines figures 7. And 8. To produce a cost per bit trend. This trend is based on the memory array density only but as long as the peripheral percentage of area stays the same should be a valid trend. It also assume that EUV enters use at 15nm. In figure 9 we have spaced out the line widths by year to more accurately show the cost trend.

Figure 9. DRAM bit cost trend. Source IC Knowledge Strategic Cost Model

For DRAM, Moore’s law is already slowing and how many generation of DRAM lie ahead is very much in question. We believe there are likely a couple more generation of DRAM before scaling stops but these generations will likely be further spaced apart in time than in the past.

It isn’t clear to us at this point what the successor is to DRAM. The only memory alternative that currently appears to have the speed and endurance to replace DRAM is MRAM and MRAM development at least to-date has been slow and it is nowhere near the density of DRAM.

Also read:
Moore’s Law is dead, long live Moore’s Law – part 1
Moore’s Law is dead, long live Moore’s Law – part 2
Moore’s Law is dead, long live Moore’s Law – part 4
Moore’s Law is dead, long live Moore’s Law – part 5

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