Tag: asics

Podcast EP347: Agentic Workflows from Caspia Technologies for Advanced Chip Security Verification with Stuart Audley

Podcast EP347: Agentic Workflows from Caspia Technologies for Advanced Chip Security Verification with Stuart Audley
by Daniel Nenni on 05-22-2026 at 10:00 am
Categories: Caspia Technologies, Security

Daniel is joined by Stuart Audley, vice president and general manager of product management at Caspia Technologies, where he focuses on agentic security workflows. He has decades of experience designing and deploying cryptographic hardware and security IP for top defense and leading semiconductor companies. He previously… Read More

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Scalable Network-on-Chip Enables a Modular Chiplet Platform

Scalable Network-on-Chip Enables a Modular Chiplet Platform
by Daniel Nenni on 04-27-2026 at 10:00 am
Categories: Arteris, IP

MOSAICS Block Diagram

The semiconductor industry is undergoing a profound transformation as system complexity, performance expectations, and time-to-market pressures continue to rise. Traditional monolithic system-on-chip (SoC) designs are increasingly giving way to modular, chiplet-based architectures that enable flexibility, scalability,… Read More

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How Switzerland Built a Global Semiconductor Edge by Thinking Smaller

How Switzerland Built a Global Semiconductor Edge by Thinking Smaller
by Admin on 02-03-2026 at 8:00 am
Categories: AI

Alain Serge Porret Headshot

By Alain-Serge Porret, Vice President, Integrated & Wireless Systems, CSEM

Since ramping up several years ago, the global semiconductor and artificial intelligence (AI) race has been driven by scale, from building larger data centers, developing bigger and more powerful models, and with them, increasingly complex and… Read More

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Outlook 2025 with David Hwang of Alchip

Outlook 2025 with David Hwang of Alchip
by Daniel Nenni on 02-17-2025 at 10:00 am
Categories: 3D IC, AI, Alchip, Chiplet, Semiconductor Services

Dave Huang

Dave Hwang joined Alchip in 2021 as General Manager of Alchip’s North America Business Unit.  He also serves as Senior Vice President, Business Development.  Prior to join Alchip, Dave served as Vice President, Worldwide Sales and Marketing for Global Unichip and in a variety of management and technical roles at TSMC.  He holds… Read More

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SmartDV at the 2024 Design Automation Conference

SmartDV at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 8:00 pm
Categories: EDA, Events

DAC 2024 Banner

SmartDV’s presence at 61st DAC centers on connections, support, and the human side of IP. Over the past 18 months, we have been laser-focused on focused on overhauling and streamlining our customer support model to provide our global IP users with the best possible service. Vice President of Application Engineering Sergio Marchese… Read More

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Using Linting to Write Error-Free Testbench Code

Using Linting to Write Error-Free Testbench Code
by Daniel Nenni on 08-23-2023 at 10:00 am
Categories: AMIQ EDA, EDA

AMIQ EDA Design and Verification

In my job, I have the privilege to talk to hundreds of interesting companies in many areas of semiconductor development. One of the most fun things for me is interviewing customers—hands-on users—of specific electronic design (EDA) tools and chip technologies. Cristian Amitroaie, CEO of AMIQ EDA, has been very helpful in introducing… Read More

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Quadric’s Chimera GPNPU IP Blends NPU and DSP to Create a New Category of Hybrid SoC Processor

Quadric’s Chimera GPNPU IP Blends NPU and DSP to Create a New Category of Hybrid SoC Processor
by Kalar Rajendiran on 11-01-2022 at 10:00 am
Categories: AI, IP, Quadric

Memory Optimization Equals Power Minimization

Performance, Power and Area (PPA) are the commonly touted metrics in the semiconductor industry placing PPA among the most widely used acronyms relating to chip development. And rightly so as these three metrics greatly impact all electronic products that are developed. The degree of impact depends of course on the specific … Read More

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CEVA Accelerates 5G Infrastructure Rollout with Industry’s First Baseband Platform IP for 5G RAN ASICs

CEVA Accelerates 5G Infrastructure Rollout with Industry’s First Baseband Platform IP for 5G RAN ASICs
by Kalar Rajendiran on 10-04-2022 at 6:00 am
Categories: 5G, Ceva, IP

PentaG RAN Massive MIMO Radio Platform

The 5G technology market is huge with incredible growth opportunities for various players within the ecosystem. As a leading cellular IP provider, CEVA has been staying on top of the opportunity by offering solutions that enable customers to bring differentiated products to the marketplace. Earlier this year, SemiWiki posted… Read More

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The Quest for Bugs: “Correct by Design!”

The Quest for Bugs: “Correct by Design!”
by Bryan Dickman on 07-04-2021 at 6:00 am
Categories: AI, EDA

Title Image

In this article we take an objective view of Virtual Prototyping from the engineering lens and the “quest to find bugs”. In this instance we discuss the avoidance of bugs in terms of architecting complex ASICs to be “correct by design”.

AI Challenges

It is not surprising to find out that other areas of human endeavour, beyond semiconductor… Read More

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CEO Interview: Rich Weber of Semifore, Inc.

CEO Interview: Rich Weber of Semifore, Inc.
by Daniel Nenni on 04-30-2021 at 6:00 am
Categories: CEO Interviews, EDA, Semifore

Rich Weber

Rich Weber co-founded Semifore in 2006 with Jamsheed Agahi. Rich has a long history of complex chip and system design at companies including Data General, Stardent, Silicon Graphics, StratumOne and Cisco Systems. He received an MS in Electrical Engineering and a BS in Computer Engineering from the University of Illinois, Urbana-Champaign.… Read More