CAST Moves the Full TCP/IP Stack into Hardware at 100 Gbps

CAST has introduced TCPIP-100G, a synthesizable intellectual-property core that implements a complete TCP/IP stack in hardware for ASICs and FPGAs. The core is designed to transmit and receive at up to 100 Gbps without depending on a host processor. That distinction is important: this is not simply a checksum engine or a network-interface block that accelerates a few expensive operations while leaving connection management to software. CAST says the core autonomously opens, maintains, and closes TCP connections, handling retransmission plus flow and congestion control inside the datapath.

For an integrating system, the programming model is comparatively simple. Firmware writes network and connection parameters into control registers, then streams application data into and out of the core. TCPIP-100G performs the protocol work needed to turn those streams into reliable, ordered TCP traffic. It can operate as either a client or server and can be synthesized to support as many as 32,768 simultaneous sessions. Because the session count is configured at synthesis time, designers can trade silicon area and memory requirements against connection density instead of paying for unused capacity.

The base configuration covers IPv4, ARP and an ARP cache, ICMP ping replies, IEEE 802.1Q VLAN tagging, checksum generation and validation, and jumbo and super-jumbo frames. Options add a DHCP client, out-of-order TCP-packet reassembly, and a UDP hardware stack with IGMPv3 multicast. A separate path can forward other IP traffic to the surrounding system. Together, these functions make the block closer to an autonomous network subsystem than a narrow transport accelerator.

CAST also exposes a meaningful architectural choice. In cut-through mode, the core begins delivering payload before the complete packet has been buffered and verified, minimizing latency and memory use. Store-and-forward mode waits for verification and delivers packets in order, favoring integrity and predictable behavior. Runtime controls cover MAC and IP addresses, filters, retransmission policy, TCP window sizes, and maximum segment size, allowing one hardware build to serve different workloads.

Integration uses familiar AMBA interfaces: a 512-bit AXI4-Stream datapath, a 32-bit AXI4-Lite or optional APB3 control interface, and a 2,048-bit AXI4 connection to external memory. Packet processing and register access occupy separate clock domains. The core is intentionally independent of the chosen external-memory technology, memory controller, Ethernet MAC, and PHY, although it can be pre-integrated with CAST or third-party MAC IP. Deliverables include synthesizable Verilog RTL or a targeted FPGA netlist, a testbench, scripts, and documentation; a UVM verification environment is optional.

Why it matters

At 100 Gbps, the line carries 12.5 gigabytes per second before protocol overhead. Processing packets, updating thousands of TCP state machines, recovering losses, and enforcing congestion windows can consume substantial CPU cycles and introduce scheduling jitter. Moving the complete stack into dedicated logic can make latency more deterministic, release processor cores for application work, and reduce the data movement and instruction overhead associated with software networking.

Those benefits are relevant to AI and high-performance-computing clusters, hyperscale infrastructure, SmartNICs, and NVMe-over-TCP storage. In each case, network processing can become a bottleneck between fast accelerators, storage devices, and memory systems. A host-independent stack also enables compact endpoints that have no general-purpose CPU, as well as appliances that need to keep moving traffic even when host software is constrained.

The practical value will ultimately depend on implementation results that the announcement does not publish: FPGA resource use or ASIC area, clock frequency, external-memory bandwidth, power, achieved throughput across packet sizes, connection churn, and performance under loss or reordering. Hardware TCP also trades software flexibility for efficiency, so standards evolution, security policy, and exceptional network conditions require careful system design. Still, TCPIP-100G represents an important option: reliable Ethernet networking becomes a configurable hardware building block rather than a software workload attached to the product.

Source: CAST, “CAST Introduces 100 Gbps TCP/IP Hardware Stack IP Core for High-Performance ASIC and FPGA Designs,” September 8, 2026.

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