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As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance,… Read More
Description
As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet… Read More
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Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include:
– Speed and power requirements lead to designs with multiple… Read More
Summary
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM.
Packaging
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In this live webinar, we will take a look at the history and revisions of JESD204 to provide an understanding of the standard, the use cases, and its future, followed by an overview of the key features of the standard, useful for system architects and system integration engineers. We will also touch on a few… Read More
Tue, Mar 1, 2022 10:00 AM – 11:00 AM PST
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The hardware/software interface, or HSI is the critical piece of technology that allows software to communicate with the hardware it’s controlling. With all the dedicated processors in most designs today, this is a very important part of the architecture.
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In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how… Read More
When I started dabbling in hardware again for fun using Arduinos about five years ago, it had been a long time since I had played with microprocessor chips. The epiphany for me was seeing how easy it was to load programs onto the onboard flash on something like an Atmel AVR using the SPI interface. My previous experience decades early… Read More
With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.… Read More
With growing size and complexity of SoC, the semiconductor community is realizing the growing pain of verification. The cost of SoC verification grows exponentially with design size. Moreover, there is no single methodology for verifying a SoC; multiple engines are used in different contexts through different verification… Read More
