LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency

LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency
by Admin on 04-06-2022 at 1:34 pm

Abstract:

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be

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Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines (EU)

Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines (EU)
by Admin on 02-16-2021 at 10:31 am

Time: 3:00 PM – 4:00 PM (CET)

Abstract:

The ALINT-PRO Static Design Verification solution includes DO-254 HDL Ruleset targeted for safety critical designs that require DO-254 compliance. Recently, this DO-254 Ruleset was enhanced with more than 80 new rules, adding a significant amount of code checks for Verilog and VHDL-based… Read More


Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (US)

Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting (US)
by Admin on 02-16-2021 at 10:30 am

Time: 11:00 AM – 12:00 PM (PT)

Abstract:

Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation

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Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (US)

Fast Track to Riviera-PRO, Part 1: Design Entry and Simulation (US)
by Admin on 02-16-2021 at 10:29 am

Time: 11:00 AM – 12:00 PM (PT)

Abstract:

Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation… Read More


Functional Verification of Clock Domain Crossing Issues (US)

Functional Verification of Clock Domain Crossing Issues (US)
by Admin on 02-16-2021 at 10:28 am

Time: 11:00 AM – 12:00 PM (PT)

Abstract:

ALINT-PRO provides powerful means for static analysis and validation of clock domain crossings(CDC). It extracts and validates clock trees, and clock domains, applying topological pattern-matching methods to validate the correctness of design structures on the clock domain boundaries.… Read More


Verifying PCIe 5.0 with PLDA, Avery and Aldec

Verifying PCIe 5.0 with PLDA, Avery and Aldec
by Bernard Murphy on 11-03-2020 at 6:00 am

little fish big fish min

Mike Gianfagna, a fellow SemiWiki blogger and a one-time colleague at Atrenta shared a useful piece of marketing advice. If your company is not the biggest fish in the pond and you want to appear more significant, team up with other companies to put on an event, say a webinar. Pick your partners so that you can jointly offer a larger,… Read More


High-Performance PCIe 5.0 IP + VIP UVM Verification Environment (US)

High-Performance PCIe 5.0 IP + VIP UVM Verification Environment (US)
by Daniel Nenni on 10-03-2020 at 4:34 pm

Abstract:

Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically… Read More


How to Build PCIe Speed Adapters for In-Circuit SoC Emulation

How to Build PCIe Speed Adapters for In-Circuit SoC Emulation
by Daniel Nenni on 10-03-2020 at 4:32 pm

Abstract:

Hardware assisted verification became much more affordable due to the availability of high capacity FPGAs such as Xilinx Virtex UltraScale US440 and their adoption for emulation verification environments. One of the advantages of FPGA-based emulation systems is that it’s much more flexible than traditional processor-based… Read More


Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two thingsRead More