Coverage is an important yet elusive metric for design verification. It often seems 90% of coverage comes with 10% of the effort, and getting the final 10% covered takes the remaining 90% of a project. Usually, it takes another tool or methodology to get at the 10% the first tool missed. With 100% closure difficult, most teams inspect what hasn’t been covered and make value decisions as to if those areas are important enough to bring in another tool and keep refining test cases.
The process of inspecting what remains uncovered may not be easy. Different tools may see and report issues differently. Accellera developed the Unified Coverage Interoperability Standard (UCIS) to create a common database of coverage and APIs for tools to share information. This is a big step; verification tools can leverage the UCISDB and standardized data models to provide a more accurate picture of total test coverage.
Like many verification tools, Aldec Riviera-PRO supports UCIS-compatible coverage databases. This allows sharing of results with other verification tools. Using the visual hierarchy in the UVM Toolbox, users can quickly navigate and inspect relationships.
This whole process seems a bit backwards, however. There were a set of design requirements, to which somebody took the effort to lay down IP to address. Then, in the process of verifying that IP actually covers those requirements, we often use a hope-based strategy that relies on how well a tool set generates test cases that cover everything – which they inevitably don’t.
What we need here is a plan. Instead of hunting around reactively for a way to cover uncovered blocks of something in a report, a proactive approach to verification would be more efficient.
If we know our design requirements, and we know our IP blocks, and we know what test methodologies, tools, and test cases provide the best coverage, we can set up verification scenarios for best results. Reporting could then link back to that test plan, replacing the question of importance with concrete coverage assessment. Experience gathered over time could be baked into these user-defined verification test plans.
In the latest release of Aldec Riviera-PRO 2014.10, the notion of user-defined verification test plans is incorporated. This creates a direct link between a requirement in the test plan and coverage results, enabling users to see if verification goals have been met. Moving away from abstract percentage coverage reports to a more proactive test flow with traceability helps verify complex designs faster.
UCIS relies on XML information exchange, so the logical path for test plan creation is a Microsoft Excel template, which can be converted to XML and imported into the coverage database. This allows merging results from simulation runs with these requirements. Test plan sections are linked with collected coverage data, and reports clearly indicate verification progress.
Giving users more control over the entire verification process with user-defined test plans is a great step. Aldec continues to refine Riviera-PRO to support a complete approach, with the ability to integrate with other verification tools and data as necessary.
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