Tag: coverage

LIVE WEBINAR: Optimizing Simulations for Efficient Coverage Collection (US)

LIVE WEBINAR: Optimizing Simulations for Efficient Coverage Collection (US)
by Admin on 10-18-2022 at 2:49 pm

Sunil Sahoo, Corporate Applications Engineer

Thursday, October 20, 2022

11:00 AM – 12:00 PM (PDT)

Abstract:

Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation,

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Coverage Analysis in Questa Visualizer

Coverage Analysis in Questa Visualizer
by Bernard Murphy on 08-10-2022 at 6:00 am
Categories: EDA, Siemens EDA

Questa coverage

Coverage analysis is how you answer the question “have I tested enough?” You need some way to quantify the completeness of our testing; coverage is how you do that. Right out of the gate this is a bit deceptive. To truly cover a design our tests would need to cover every accessible state and state transition. The complexity of that task… Read More

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Hybrid Verification for Deep Sequential Convergence

Hybrid Verification for Deep Sequential Convergence
by Bernard Murphy on 02-26-2020 at 6:00 am
Categories: EDA, Synopsys
2 Comments

Hybrid Verification Synopsys

I’m always curious to learn what might be new in clock domain crossing (CDC) verification, having dabbled in this area in my past. It’s an arcane but important field, the sort of thing that if missed can put you out of business, but otherwise only a limited number of people want to think about it to any depth.

 

The core issue is something… Read More

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How Good is Your Testbench?

How Good is Your Testbench?
by Bernard Murphy on 01-29-2020 at 6:00 am
Categories: EDA, Synopsys
2 Comments

Limitations of coverage

I’ve always been intrigued by Synopsys’ Certitude technology. It’s a novel approach to the eternal problem of how to get better coverage in verification. For a design of any reasonable complexity, the state-space you would have to cover to exhaustively consider all possible behaviors is vastly larger than you could ever possibly… Read More

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An Advanced-User View of Applied Formal

An Advanced-User View of Applied Formal
by Bernard Murphy on 03-08-2018 at 7:00 am
Categories: Events, Oski Technology, Semiconductor Services

Thanks to my growing involvement in formal (at least in writing about it), I was happy to accept an invite to this year’s Oski DVCon dinner / Formal Leadership Summit. In addition to Oski folks and Brian Bailey (an esteemed colleague at another blog site, to steal a Frank Schirrmeister line), a lively group of formal users attended… Read More

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Quantifying Formal Coverage

Quantifying Formal Coverage
by Bernard Murphy on 05-03-2017 at 7:00 am
Categories: EDA, Synopsys

Verification coverage is a tricky concept. Ideally a definition would measure against how many paths were tested of every possible path through the complete state graph, but that goal is unimaginably out of reach for any typical design. Instead we fall back on proxies for completeness, like hitting every line in the code. This … Read More

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Webinar: Getting to Formal Coverage

Webinar: Getting to Formal Coverage
by Bernard Murphy on 04-20-2017 at 10:00 am
Categories: EDA, Synopsys

Facing rapidly growing challenges in getting to respectable coverage, designers have been turning more and more to formal verification, not just to plug gaps but increasingly to take over verification of significant components of the testplan. Which is great, but at the end of the day any approach to verification must be measured… Read More

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Bringing Formal Verification into Mainstream

Bringing Formal Verification into Mainstream
by Pawan Fangaria on 04-28-2016 at 7:00 am
Categories: EDA, Synopsys

Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More

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Cadence Adds New Dimension to SoC Test Solution

Cadence Adds New Dimension to SoC Test Solution
by Pawan Fangaria on 02-04-2016 at 7:00 am
Categories: Cadence, EDA

It requires lateral thinking in bringing new innovation into conventional solutions to age-old hard problems. While the core logic design has evolved adding multiple functionalities onto a chip, now called SoC, the structural composition of DFT (Design for Testability) has remained more or less same based on XOR-based compression… Read More

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A Robust Lint Methodology Ensures Faster Design Closure

A Robust Lint Methodology Ensures Faster Design Closure
by Pawan Fangaria on 06-03-2015 at 4:00 am
Categories: EDA

With the increase in SoC designs’ sizes and complexities, the verification continuum has grown larger to an extent that the strategies for design convergence need to be applied from the very beginning of the design flow. Often designers are stuck with never ending iterations between RTL, gate and transistor levels at different… Read More