With advances in available IP, mixed signal design has become much easier. Mixed signal verification on the other hand is becoming more complicated. More complexity means more simulation, and in the analog domain, SPICE-based techniques grinding away on transistor models take a lot of precious time. Event-driven methods like Verilog in the digital domain are very fast, but do little with the analog IP.
Ideally, behavioral simulation could encompass both analog and digital domains. Verilog-A provides equation-based definitions of analog behavior, resulting in a faster model than SPICE. A working assumption is SPICE would be used to thoroughly simulate analog IP blocks, and they would be fully verified before heading into the mixed signal environment. This implies a higher-level behavioral model would be suitable for SoC integration and verification.
Such a new model is here. Accellera has released a new specification, Verilog-AMS, fully embracing Verilog-A and harmonizing the digital and analog capability. SystemVerilog under the purview of the IEEE may evolve and consume the entire chain for mixed signal design and verification needs, but that is years off.
Any methodology takes time to develop and be fully supported with integrated EDA tools. Reality today is there are great SPICE simulators, awesome Verilog simulators working against RTL in digital domain (Verilog-D as referred to informally), and some Verilog-AMS capability. How can these work together on a mixed signal design?
One way is to attempt to create IP stunt doubles – cross-domain models representing a block in the other domain, so separate simulation passes in the analog and digital domains would be more complete. For instance, one could create a Verilog-D model of an analog block to approximate its operation. That may be a full design and manual verification effort unto itself for a complex analog IP block. At least some information could be gathered in digital simulation.
The other direction is much more problematic and less rewarding. A complete SPICE model of a complex digital IP block, presuming you can obtain or write one, would be excruciatingly slow in an analog simulation. Assuming the IP vendor and foundry have done their jobs, little new insight would be gained on the digital blocks, but a huge amount of time would be expended.
Tanner EDA and Aldec have been refining the connection between their tools for mixed signal simulation. Tanner T-Spice is aware of the full mixed signal design and delivers the analog simulation, and Aldec Riviera-PRO provides the digital simulation. Pre-processing handles the splitting between the domains, and connect modules written in Verilog-AMS handle the interpretation of signals between the simulators.
A recent joint webinar explores the idea further. It offers a quick overview of some Verilog-AMS concepts, some background on the tools themselves, and a demonstration of the connected suite of T-Spice and Riviera-PRO in examining an 8-bit successive approximation A/D.
(Pro tip: If you are already familiar with Tanner EDA and Aldec, you may want fast forward to the 11:20 mark of the archived event where technical discussion begins.)
The potential for this approach is remarkable. Both T-Spice and Riviera-PRO are extremely well trusted in their respective domains; rather than develop an all-new, unproven tool for Verilog-AMS, using these two tools together results in a lower learning curve and reliable results. It also allows full capability of each tool to be brought to bear on mixed signal designs, including scalability to the limits of both simulators.
With Verilog-AMS specifications stabilized and Tanner and Aldec capabilities well-tested and continuing to improve with new features, this approach to mixed signal verification has low risk and a quick ROI for designers.