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An Approach to Top-Down SoC Verification

An Approach to Top-Down SoC Verification
by Daniel Payne on 12-19-2014 at 1:00 pm

We’ve blogged dozens of times about UVM– Universal Verification Methodology at SemiWiki, and all of the major EDA vendors support UVM, so you may be lulled into thinking that UVM is totally adequate for top-down SoC verification. Yesterday I had a phone discussion with Frank Schirrmeister of Cadence about a new approach to top-down SoC verification that has started to change my mind because they have engineered a new EDA product called Perspec, announced just last week.

An SoC is really part of a larger system which contains IP blocks, cores, operating system, drivers and apps.


Typical SoC

Related – Don’t Mess with SerDes!

If you need to bring up an OS early for validation, then how would you do it? Let’s say that your SoC has 150 IP blocks and 8 processors – how do you deal with coherency, power, OS, measure all of your verification tests, and re-use IP verification? The new approach from Cadence has you creating an abstract model in UML (Unified Modeling Language) for each use case, then run constraint solvers to automatically create software tests from a top-down perspective.


Perspec System Verifier

The above block diagram shows how four tests have been generated to run on the cores of an SoC. To create a new use case there’s a graphical approach in Perspec with UML:


UML based use-case: View a video while uploading it.

Related – Semiconductor IP Information Flow

Once the use-case is defined, then the solver goes to work and creates a constrained random data and control flow for you, automatically saving much manual effort.


Results of solver

Another use case could be to decode video from the DDR and show it on the display, so using SLN (System Level Notation) and UML this can be entered and then the solver will automatically and exhaustively complete the goals into full, legal scenarios.


DDR use case

The five steps in using Perspec are show below, and you can use any vendor tool for: Virtual Platform, Simulation Platform, HW acceleration and emulation, FPGA prototyping.


Use case verification flow

With this top-down verification approach you can even model complex behaviors like running cache transactions during power shutdown of one core, while powering up another core to validate coherency.

Related – Using Cadence PVS for Signoff at TowerJazz

The development of Perspec was all done in-house at Cadence over several years by the same engineering team that created Verisity. If you visit DVCONin March 2015, then check out a paper by STmicroelectronics: Automated Test Generation to Verify IP Modified for System Level Power Management. Cadence will also have a tutorial: Verification Solutions for ARM v7/v8 Based Systems on Chips.

Summary

Using this new top-down approach to SoC verification can benefit your development team by:

  • Abstraction – create use cases with UML style diagrams with debug tied in
  • Automation – solvers automatically create complex tests
  • Platforms – run more tests on pre-silicon and post-silicon platforms
  • Measurement – know the coverage of functionality, flows and dependencies
  • Leverage – reuse use cases across different users
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