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A Brief History of Silicon Frontline

A Brief History of Silicon Frontline
by Paul McLellan on 12-19-2014 at 7:00 am

 Silicon Frontline was founded in 2007 by Yuri Feinberg. Since then the company has built up a team with expertise in computational geometry, circuit layout, circuit simulation and analysis, and post-layout verification. After a small initial funding, Silicon Frontline has continued to grow, acquiring new customers even over the last few years of macro-economic uncertainty. The first products, F3D and R3D, were released in 2009. F3D is used for reference extraction (against which other extractors are compared during qualification of new processes) and high-accuracy RC extraction (needed in, for instance, image sensors). R3D is a unique product for power transistor verification and optimization. R3D was extended to optimization of the gate network in 2010, and further extended to incorporate a high-performance thermal analysis engine in 2013.

Silicon Frontline has leveraged their core technology into new product lines (ESRA, P2P and P2P-XL) which were launched in 2012 to address the needs of large AMS or SoC designers, considering interconnect behavior under IR drop, current density/electromigration and ESD. SoCs on leading-edge processes have increasing challenges in these areas. A strong driver with minimum width metal at the output is already out of spec for electromigration. And ESD is no longer a problem limited to the I/O devices.

The roots of the company are in Nassda, Silvaco, PDF and other companies. The founder and CEO, Yuri Feinberg comes via Nassda, Epic and Silvaco. The COO Dermott Lynch was at Infinisim, Nassda, and Sente. The CTO Maxim Ershov from Foveon, T-RAM, PDF Solutions, and was a professor at Georgia Tech and at University of Aizu (in Japan).


The basic premise of the company is that:

  • Design is moving to AMS – modulators everywhere, usually switch-cap, with lots of digital control for calibration and compensation. Both absolute and relative accuracy are required
  • Post-layout verification isn’t keeping up with the demands of new processes. There’s plenty of work on the process side, and on the layout/design creation side, but marrying the two requires too many shortcuts and approximations that inject errors and inaccuracy into the verification procedures
  • Tape out times are lengthening. Respins continue to be the norm. There’s lots of focus on next gen devices (FinFETs, and new passive structures too, like MIM/MOMs) and not enough on verifying the interconnect
  • Focus on ease of use for neophyte or infrequent users, with plenty of power available, and ease of results visualization

Despite their low profile, not quite stealth mode, they do have customers, over 40 of them, including 9 of the top 20 semiconductor vendors. The products are used in a wide range of different applications: power devices, smart power, image sensors, flash memories, network devices, controllers, HSIO, PLL/DLL, data converters, analog/mixed-signal circuits. They are supported on all contemporary processes by all major foundries.

Silicon Frontline’s website is here.

More articles by Paul McLellan…


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