WP_Term Object
    [term_id] => 105
    [name] => Silicon Frontline
    [slug] => silicon-frontline
    [term_group] => 0
    [term_taxonomy_id] => 105
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 4
    [filter] => raw
    [cat_ID] => 105
    [category_count] => 4
    [category_description] => 
    [cat_name] => Silicon Frontline
    [category_nicename] => silicon-frontline
    [category_parent] => 14433

Analyzing Power Nets Early and Often, a New White Paper

Analyzing Power Nets Early and Often, a New White Paper
by Paul McLellan on 02-22-2015 at 7:00 am

 One of the big challenges in designing ICs today is designing a robust power net capable of delivering necessary current levels to all areas of the die. Getting it wrong can, of course, lead to circuit failures that range from non-functional silicon, through intermittent performance and functional problems, to early EM-driven failures. Designers carefully perform accurate power net analysis before tapeout. However, finding problems this late in the design cycle can result in schedule slips if anything more than a trivial fix is required.

Large SoCs have complex and widely-distributed power nets, but since most of them are constructed by automated place and route they tend to have fewer late issues. They also are less amenable to early analysis since every time the design is re-placed pretty much everything changes. Furthermore, with 10 or more layers of metal, some of which are very low resistance, the problem is just not so acute.

But analog/mixed-signal ICs, memories and image sensors have many fewer layers of metal, and sometimes these are narrower (by design necessity) and of lower quality (higher resistance) materials. In addition, often these designs use complex non-orthogonal routing of power nets, which can complicate extraction and analysis for some verification tools. Obviously, eventually the power has to get down to the transistors and as a result power often has to be distributed at least partially on low levels of metal. But these low levels of metal are narrower and so resistance is more of an issue.

 This is where Silicon Frontline’s P2P (which stands for “point to point”) comes in. It allows for extremely fast analysis of power nets very early in the design. It can even start to give preliminary analysis before the layout is complete. It does an accurate calculation of the resistance between any two points or groups of points (hence the name) with various resistance-map displays that allow the designer to quickly zoom into the issues where the resistance is very high (just look for the bright red regions in a sea of blue).

 The tool is very easy to configure, very fast and has essentially unlimited capacity. Where the tool really shines is on analog/mixed-signal, memories, image sensors and other designs where the power nets, because of their complexity and all-angle shapes, often require manual intervention. The resistance mapping mode of P2P can be used on incomplete layouts, or during layout development in the architecture and partitioning stage of design. And then, when the design is complete and P2P resistance mapping has been used to ensure that all power nets are low resistance and any simple problems have been fixed, the designer can perform detailed IR drop and electromigration (EM) analysis with a good candidate design. If all resistances are low then IR drop will be low (or lower) by definition and typically EM is less of an issue too, since low resistance metal tends to be wider.

A new white paper is now available that covers P2P in detail including an example of its use to track down some errors in the design and take a power network from a resistance of 30 ohms, way too high, down to a resistance of just over 3 ohms in a matter of minutes.

The white paper can be downloaded here.

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