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Full-chip Multi-domain ESD Verification

Full-chip Multi-domain ESD Verification
by Paul McLellan on 03-27-2015 at 7:00 am

 ESD stands for electro-static discharge and deals with the fact that chips have to survive in an electrically hostile environment: people, testers, assembly equipment, shipping tubes. All of these can carry electric charge that has the “potential” (ho-ho) to damage the chip irreversibly. Historically this was a problem only for I/O pads which had to take care to dump the unwanted influx of charge without harming any of the on-chip transistors. There are three models for the aggressor, almost always just identified by their acronyms: human body model (HBM), machine model (MM) and charged device model (CDM). They all inject charge in various well-specified ways, using circuits involving capacitors, resistors and inductors.

In modern chips, with thinner gate oxides and multiple power domains, ESD is not an issue confined to the pad-ring. ESD protection devices need to be included in the core. Of course many chips are bumped and in that case the pads are often not confined to the “pad-ring” since there is none, but even chips where the pads are at the edge of the chip can suffer internal failures from ESD. The ultimate way to check ESD is with a real chip and real ESD test equipment, but obviously, except in the case of a test-chip, that is too late to address any issues.

ESD cells and devices such as diodes, transistors, clamps, and so on, consist of a large number of elementary devices that are interconnected by metal layers to provide sufficient ESD protection. Detailed understanding of the current flow and potential distributions in these interconnects and devices is important to optimize the device layouts and to ensure a balanced current distribution, low resistance, and efficient connection of devices to power nets. Standard parasitic extraction and simulation approaches are inadequate to describe these effects.

Silicon Frontline’s ESRA (ElectroStatic Reliability Analysis) fills this gap and provides a full-chip ESD analysis solution. It delivers extraction, analysis and debugging capability in one integrated environment with the capacity to analyze the full chip. Highlighted violations permit designers to perform corrections at any time in the design process.

ESRA builds on production-proven technologies, including fast and guaranteed accurate parasitic extraction and circuit-proven, high-capacity matrix solvers. Layout based, full-chip visualization and debugging of current density and potential distribution is included, and the whole solution is seamlessly integrated within existing layout flows.

ESRA automates verification of ESD protection networks for electrical connectivity, resistance, and current density checks. It:

  • replaces manual ESD checks with well defined automated checks
  • offers a new verification methodology that quickly identifies issues in the layout, and analyzes weak elements of ESD network
  • provides a detailed (mesh-based) simulation and analysis of ESD protection devices and network elements, ensures the efficiency of electrical connections, and their compliance with current density and resistance rules
  • enables early capture of ESD protection problems avoids expensive silicon re-designs and re-spins

Problems can be displayed graphically annotated onto the layout by highlighting problem areas using color.

In summary, ESRA verifies that ESD design guidelines are met, highlights weak areas of designs, reports current density violations and high resistance paths. Details of ESRA are on Silicon Frontline’s website here.

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