Applications for IoT sensors are becoming more sophisticated, especially for industrial usage. Building optimal sensors for different applications requires multi-domain design, optimization and verification flows. The sensor devices are usually MEMS, and as such have electrical properties that need to be tailored to the analog circuitry they are connected to. Many MEMS devices are not completely passive: they often have drive systems to keep them in their most linear range of operation. For example an accelerometer will have two comb capacitors, one is for sensing, the other is to control the proof mass.
Cadence, Coventor and ARM recently held a webinar that showed how many important considerations in designing an industrial IoT sensor node can be addressed. The full session is available here.
In these designs the analog circuity needs to be designed and optimized at the same time as the MEMS structures. Chris Welham, Worldwide Applications Engineering Manager at Coventor, points out in the webinar that Coventor offers their MEMS+ product as a vehicle for building 3D design of MEMS elements in conjunction with circuit design tools. The key to making this effective is that after the MEMS designer creates a device, they can export it to Cadence, where it is represented as a parametric simulation model, symbol and PCell. The parameters exposed to the circuit designer are specified when the MEMS+ model is generated. This means that the circuit designer can alter specific parameters of the MEMS device easily and independently. In the webinar Cadence showed how Virtuoso ADE GXL can be used to concurrently optimize the circuit and MEMS parameters to meet the system design spec. The PCell that is produced by MEMS+ produces the necessary layout for mask generation.
IoT sensors need to be compact, rugged and have battery life considerations. These needs often drive the specific packaging configuration for the various SOC’s and MEMS chips in the unit. Designers can utilize BGA, bond wires and TSV’s in an assortment of configurations that can include stacked die with silicon interposer. In the webinar Ian Dennison, Solutions Group Director at Cadence, shows examples of each of the 3D-IC approach alternatives and highlights design and verification aspects of each.
For designs with bond wires, stacked die present special challenges. Manufacturing and coupling noise considerations play a major role in wire placement and shape. Cadence SIP allows wire profiles to be defined and then viewed in 3D. The webinar showed several examples where wire profiles need to be configured to provide adequate clearances to avoid things like overhanging shelves or neighboring wires.
TSV’s offer many advantages over bond wires, but working with them adds complexity to the chip design process. First off, on the plus side, TSV’s reduce overall system cost. On-chip they save routing resources that would otherwise be needed to get signals to the chip boundary and they lower parasitic capacitance and inductance. However the chip floorplan must account for their location. In the webinar Cadence discussed how Encounter and Virtuoso let designers work with TSV’s.
Tim Menasveta, CPU Product Manager at ARM went last but covered the critical aspects of how creating a sensor hub in the IoT sendor device can help the IoT senor meet its many design requirements. Without a hub, all the raw sensors would be transmitting to the aggregation point continuously. This wastes power and bandwidth. Instead with a local processor the IoT sensor node can decide when and what data should be sent. Additionally sensor fusion is extremely important. Many of us are familiar with the necessity of combining the raw inputs from a gyroscope and accelerometer to obtain accurate real world results. Also temperature is an important input for most sensor interpretation. Sensor fusion is useful for dealing vibration or effects of nearby iron objects when calibrating a compass.
The new Cortex-M7 boasts an improved DSP and floating point unit when compared to its predecessor the Cortex-M4. The M7 is ideal for bare metal code. The M8 is more suitable for higher level OS’s. There is also an optional double precision floating point unit available for the M7. To facilitate development of designs using the Cortex-M7, Cadence and ARM have collaborated on an implementation reference methodology built on TSMC’s 40LP process. This design uses Physical IP by the ARM Physical IP Division. It is a low power design that has support for power gating.
The webinar pulled together a wide range of technology, all of which is necessary for putting together leading edge IoT sensor based designs. For a more in depth review of the technology,I suggest following the link at viewing it.Share this post via: