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Making Things Visible for 25 Years

Making Things Visible for 25 Years
by Paul McLellan on 06-03-2015 at 7:00 am

 This year is most notably the 50th anniversary of Moore’s Law. It is also the 25th anniversary of Concept Engineering. They were founded in 1990 in Freiburg Germany. They started by providing automatic schematic generation from netlist. They sold primarily to other EDA companies and to internal development groups in semiconductor and system companies. As synthesis became the dominant methodology for digital design in the 1990s, it became necessary to visualize the output of synthesis. The challenge was to make a schematic from a netlist in a way that was understandable by the designer. Just randomly throwing the gates on the screen and hooking them up with wires wouldn’t work. Concept became the standard for doing this and pretty much every EDA company (except Synopsys which created their own viewer earlier) standardized on Concept’s viewer. When I was VP engineering at Ambit in the late 1990s, we used it too. I was by no means alone, they have over 40 OEM customers in the EDA and semiconductor markets (including FPGA).

With the growth of IP-based design in the 2000s to today, the need to take netlists of various kinds and visualize them became even more important. IP from 3rd parties and even from other groups inside the same company needed to be understood by the designers building the SoCs, so that they could use the IP correctly and, often, remove functionality from the IP that was not required on that design. So Concept started to sell tools for visualizing netlists, RTL, transistor netlists and system. Over 250 chip design companies have licensed Concept’s VISION line of customizable products to debug digital, analog and mixed-signal designs.

 As the company’s tag-line says “We make things visible.”

It is impossible to argue with Gerhard Angst, Concept’s CEO, when he says:
A quarter of a century is a significant milestone for any technology company. We could not have reached this milestone without the continued support and trust of our customers, and the passion and commitment of our staff.

But they are not just blowing out candles on their birthday cake, they have a complete new release, version 6, of their product line. This will be on show next week at the DAC on booths 2208 and 2210. You can see the latest releases of StarVision PRO, RTLvision PRO, GateVision PRO and SpiceVision PRO.

What’s new in version 6? Some notable enhancements are:

  • Improved netlist pruning: In addition to Verilog and SPICE netlist export and pruning, StarVision PRO now also allows netlist pruning for the most common post-layout formats, DSPF and SPEF.
  • Advanced post-layout debugging: Improved visualization and debugging of parasitic networks.
  • API improvements: Improvements in the database API and GUI API allow even more sophisticated code to be developed and executed by the tool.
  • Advanced batch processing: Enhanced batch processing capabilities allow more efficient processing of user-defined analysis and debugging tasks.
  • Unified File Open Dialog: Makes it easier to load complex mixed-language SoC designs and libraries.
  • Improved visual debugging capabilities such as: Smart connectivity lens view, improved schematic navigation history, and on-the-fly hierarchy exploration with built-in fold and un-fold controls.

 As an example of how other EDA companies use Concept’s technology as a foundation, earlier this week Aldec and Concept Engineering announced that Aldec’s ALINT-PRO-CDC clock-domain crossing verification tool is using Concept’s Nlview schematic visualization engine. This allows the tool to combine Aldec’s advanced analysis with Concept’s easy-to-read schematic diagrams to create an advanced debugging cockpit for tracking down and fixing clock-domain crossing problems.

The press releases are:

  • 25th anniversary here
  • Version 6 of the product line here
  • Aldec’s clock domain crossing solution here

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