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Enabling Higher Level Design Automation with Smart Tools

Enabling Higher Level Design Automation with Smart Tools
by Pawan Fangaria on 08-02-2014 at 10:00 pm

Although design houses have always strived for optimizing best design flows according to their design needs by customizing the flows using effective and efficient internal as well as external tools, this need has further grown in the context of design scenarios getting wider and wider from transistor, gate and RTL to system level. Today, it’s rare a single flow connects the system up to transistor in terms of design, verification or debugging; however comprehensive methodologies are must at all these levels to reflect the effect of any change at transistor, gate or interconnect level up to the system level, or let’s say IP level which is integrated into an SoC.

A couple of weeks ago I was talking about Concept Engineering’sS-engine[SUP]TM[/SUP] which could be easily integrated into any design automation tool for automatic schematic generation (and smart editing) that could enable transistor, gate or SoC/IP interface visualization at any level of abstraction in the design for efficient design and system exploration, analysis, debugging and integration. After learning that Verific Design Automation, Alameda, CA has integrated Concept Engineering’s Nlview[SUP]TM[/SUP]schematic generation and visualization engine with their netlist database (press release here), I looked a bit deeper into Nlview and this integration.

Nlview Widgets is pioneered by Concept Engineering which is used to automatically generate and visualize schematic diagrams at various levels in the design process including transistor (with electrical components), gate, RTL or complete block and system. The schematics thus created can be interactively controlled and modified by designers as per their need, with a capability to incrementally generate and further add parts of schematics.

Look at the part of schematic using operator signs with bus connectivity (which may come from any third party parser). The Verific parser (SystemVerilog, VHDL…) and VVDI-link(connectivity package provided with Nlview software package) give Nlview seamless access to the Verific netlist database.

In this schematic with busses, the rippers are automatically created. The Nlview performs automatic net bundling from the connectivity with single-bit level. The IO port buses and the bus pins of the muxes need to be indicated to Nlview.

In this schematic, signals are passing through hierarchical blocks. The Nlview provides features such as putting the blocks in different colors, folding and unfolding of hierarchy with +/- signs, incremental navigation and so on.

There are host of other features including timing annotations, incremental generation and viewing, and others. More examples of schematics can be seen here. The schematics are optimized by using robust, fast algorithms.

The Nlview Widgets are customized according to different GUI environments such as NlviewQT for Qt development environment, NlviewTK for Tcl/Tk based GUI environment and so on. Today, Concept provides NlviewQT, NlviewTK, NlviewJA (for Java platform), NlviewMFC (for MS Windows platform based on MFC library), NlviewWIN (for MS native Windows), NlviewWX (for wxWidgets cross-platform), NlviewP TK (for Perl with Tk) and NlviewCORE. The NlviewCORE is without GUI which can output graphic files like SVG, PostScript or PDF in batch mode. The provided core APIs and algorithms are same in all of them except the GUI interfaces.

By integrating Nlview schematic generation in EDA applications such as high level synthesis or logic synthesis, verification, physical design, test automation etc. designers or tool owners can enhance their tool’s capability in terms of wider and deeper navigation, performance, on-the-fly IP/block management and integration, incremental schematic generation and viewing, greater control and visibility over the synthesis process, easy and integrated debugging environment and so on, thus improving designers productivity.

The VVDI-Link in the connectivity package, aided by standard Verilog, VHDL or SystemVerilog parsers from Verific, enables automatic generation of schematic through Nlview for Verific which acts as front-end for several EDA and FPGA tools for simulation, emulation, verification, synthesis, analysis and test of RTL designs.

With 10s of thousands of installed EDA applications using Nlview Widgets, it’s clearly an industry standard for schematic generation and viewing that provides unparalleled flexibility, customizability, controllability, performance and reliability to the integrators.

More Articles by Pawan Fangaria…..