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Carnegie Robotics Case Study: RTLvisionPRO

Carnegie Robotics Case Study: RTLvisionPRO
by Daniel Nenni on 09-04-2019 at 10:00 am

RTLvisionPRO has proven to be an indispensable tool which has greatly improved the productivity and work-flow of our current task: understanding, verifying, and documenting the existing RTL IP library at our company. Consisting of about 500 Verilog and VHDL files, the library has been under development for several years and implements a multitude of image-processing modules and pipelines used in our current sensor and peripheral products. While well-tested and vetted, most modules in the library lack an in-depth level of documentation that is needed for effective re-deployment in new products. Our task has been to carry out a critical review of the library modules and to create a detailed set of documents which convey the deep knowledge necessary to understand their implementation and function.

Webinar: Desinging Complex SoCs and Dealing with Multiple File Formats?

As expected, the task has been overwhelming and difficult. Perhaps a complicating factor is the fact that the same FPGA serves multiple purposes in different products and peripherals. Many pins have multiple functions with a significant percentage remaining unused in each implementation. Working through the design by tracing from signals can be quite time consuming. One needs to navigate from file to file tracing signals and nodes in an effort to understand how the design works. This is a tedious task as steps need to be documented while traversing from module-to-module. RTLvision essentially does all the tedious parts of this task. It has a seamless interface with which one can navigate through the design. It keeps track of every step along the way so you can step back and forth and record the appropriate snapshot for documentation. If you go through something unimportant, you can simply go back to where you were before you took the wrong turn. This is an outstanding feature. It also supports bookmarks so you can jump to strategic places quickly.

The typical first step in understanding an existing design is to get a top-level picture of the entire system. This requires a comprehensive capture and representation of the design, all in one place. We were able to import the entire code base into RTLvision using a simple script which listed the directory paths to the libraries and the RTL design files themselves. The tool crunched on the files and returned with a set of top-level designs it found in the provided files. This was surprisingly simple and quick. After the importing stage, the tool builds a database which can be saved to a file eliminating the need to reimport the files. The database of our 500-file design loads in seconds.

The global schematic view given by all FPGA tools is not particularly useful. Essentially, you see a schematic view similar to the figure above. A number of modules are connected by millions of undiscernible connections. Tracing through that is basically impossible. We needed a tool to show the modules but help us trace signals as we work our way through a data path. This is exactly where RTLvision shines. Using the Cone view, you can focus on the parts of the path you are interested in and not display all the clutter from all adjacent nodes and signals. This is a powerful feature of the program. You can see more and more detail by repeatedly clicking on the traced signal. If you click too many times, uncovering uninteresting parts, you can always go back where you were before using the back arrow.

You can quickly generate schematic diagrams which are derived from the RTL files. You can move things around or have the program place components in a sensible orientation to make a clear diagram similar to the one above.

We continue to learn about the other debugging and analysis features of the program. But simply for going through and understand the bulk of a large design, RTLvisionPro has been an indispensable tool.

Omead Amidi, Ph.D.

Carnegie Robotics, LLC
4501 Hatfield Street
Pittsburgh, PA 15201

Webinar: Desinging Complex SoCs and Dealing with Multiple File Formats?