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Complete SoC Debugging & Integration in a Single Cockpit

Complete SoC Debugging & Integration in a Single Cockpit
by Pawan Fangaria on 11-15-2014 at 10:00 am

These days it’s common to expect large digital designs, analog blocks, custom IPs, glue logic, interfaces and interconnects all developed separately, perhaps by different vendors / teams, but integrated together in a single environment forming an SoC. The SoC can have multiple clock domains and can work in multiple modes of operations. Although different parts of the SoC may have been validated by respective teams, it becomes most difficult to understand all those components and verify all of them together at the time of integration in a single environment. Also, it’s gruelling keeping track of changes done by optimization, test and other tools. So, definitely, there arises the need for a versatile, intelligent tool and environment which can help easing pressure of debugging various parts of a design at different levels, interfaces and customizations in a single cockpit.

While attending a webinarpresented by Gerhard Angst of Concept Engineering, it was clear that StarVision PRO provides the right kind of platform for analyzing and debugging today’s SoC designs. It has a complete digital interface for reading designs (either at RTL or at netlist level) in Verilog SystemVerilog, VHDL, LEF, DEF, and EDIF and so on along with various settings and options. The analog interface includes all Spice dialects, CDL, Spectre, Calibre, Eldo, SPEF, DSPF, and RSPF and so on. There is an expert cmd line interface which can read designs in different formats (such as Verilog, EDIF, Spice etc.) in succession, compile and merge RTL, netlist and Spice together and load the overall compiled design to view in the GUI.

Multiple views along with simulation data annotated with the respective components and a separate waveform view can be seen at once in a single GUI. The waveform viewer can also be invoked separately to review large simulation data with particular, components, IOs or ports.

In an SoC design, it may be possible that particular design blocks are not ready. A beauty of StarVision environment is that it supports top down design methodology by keeping the incomplete blocks and code for the same in ‘gray’ to be filled in later.

A Clock Tree Analyzer can show a complete clock tree along with its interconnect logic. All clock domains can be viewed and their crossings can be analyzed at ease by using various available search options.

The RTL can be visualized in free schematic, Process (for VHDL) or Always (for Verilog) styles while the RTL code remains the same. It might be possible that a VHDL Process code may be driving a Verilog Always code.

Connectivity Lense is a great debugging feature which can expand connections to any port, and this can continue up to any level till the full path is traced. This feature works at all levels; RTL, Gate or Spice. At the Spice level, it can show all the transistors hidden with M-factor along with their connections. There is another path extraction feature which can extract and show a complete path between two ports or path(s) between a port and instance(s) of certain type. It can be used in various ways as desired.

In a complex mixed-signal design, understanding and debugging Spice netlist is the most difficult task. StarVision provides multiple options such as netlist reduction (by merging transistors in series or parallel, parallel capacitors, serial resistors and so on), hiding the parasitics from the netlist, and automatic logic recognition to simplify a Spice netlist, thus making it easy for a designer to view and understand the Spice netlist.

StarVision uses smart schematic generation algorithm; designers can switch between analog and digital schematic types to manoeuvre between different designs styles within an SoC.

Post layout debugging, another difficult task, is supported by easy visualization and export of critical paths with netlists including resistances and capacitances. All formats including SPEF, RSPF and DSPF are supported. The extracted parasitic netlist can be viewed separately along with the transistor netlist. Any identified part of a circuit can be written out as Spice or Verilog for separate analysis and debugging, as is done for an IP.

The StarVision environment also supports a number of UserWare APIs customized for designers’ productivity. Concept Engineering supports with the source code and documentation of these APIs for designers to develop their own new customized APIs or use the existing ones.

The webinarcan be viewed for detailed information and also a nice demo on a design. Concept Engineering tools & technologies are also being exhibited at SemIsrael Expo 2014by their distribution partner KAL Katav Associates Silicon Technologies Ltd.

Visit Booth #36 at –
SemIsrael Expo 2014 Exhibition
Avenue Convention Center at Airport City, ISRAEL
November 25, 2014

Contact info@concept.de and sales@edadirect.com for any more information.

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