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Debugging SoCs at the RTL, Gate and SPICE Netlist Levels

Debugging SoCs at the RTL, Gate and SPICE Netlist Levels
by Daniel Payne on 10-02-2019 at 10:00 am

Debugging an IC is never much fun because of all the file formats used, the levels of hierarchy and just the sheer design size, so when an EDA tool comes around that allows me to get my debugging done quicker, then I take notice and give it a look. I was already familiar with debugging SPICE netlists using a tool called SPICEVision Pro, but hadn’t spent much time learning about Gate and RTL debugging automation tools. Perfect timing, because EDA Direct organized a webinar recently on this very topic, so I signed up and will share what I learned.

Our webinar presenter was an AE named Sujit Roy from EDA Direct, and he has plenty of hands-on experience debugging designs at the RTL, Gate and SPICE netlist levels. The four products from Concept Engineering that were discussed and shown included:

  • RTLvision Pro – RTL debugging (Verilog, SystemVerilog, VHDL)
  • GateVision Pro – gate-level netlist debugging: Verilog, EDIF 2.0.0, LEF/DEF, Liberty, VCD, SDF
  • SpiceVision Pro – SPICE netlist debugging: HSPICE, Spectre, CDL, Calibre, Eldo, SPICE, SPEF/DSPF
  • StarVision Pro – All three of the previous tools, combined

By debugging, I mean the act of reading in netlist files, then graphically viewing, filtering and examining portions of a design throughout its hierarchy to understand the connectivity. Sujit first demonstrated RTLVision Pro by reading a digital design from Open Cores, then traversing the hierarch using a tree widget in the left pane, while showing the auto-generated schematic in the right pane:

Concept Engineering - auto schematic

Sure, using a text editor you can view an RTL design, but you won’t understand the connectivity or be able to trace a signal path as quickly as a graphical tool. In the above diagram a net called RXD was selected and highlighted, in order to understand which block drives RXD, and which blocks read RXD. The tool allowed us to create a cone of logic starting from RXD and going any direction we wanted to explore.

Concept Engineering - expanding cone of logic
Logic Cone

RXD was driven by a FF cell, so we looked inside the FF cell and could view the source code in another pane. The Clock signal to the FF was selected and we could view all of the cells that used Clock, while hiding other signals to improve clarity.

Concept Engineering - source code pane
Source Code

The drop-down menus had plenty of useful commands, and you can even run any of the 100 or so pre-built Tcl scripts. CAD groups can extend or even modify these Tcl scripts to automate design-specific debugging. SPICE netlists can be loaded, viewed and traversed:

Concept Engineering - SPICE view
SPICE Netlist

During the demo we saw a mixed-signal design that had an Analog block called Parity, along with a digital block called CPU:

Concept Engineering - mixed signal
Mixed-Signal Design

Even netlists that have extracted parasitics from a SPEF file can be quickly loaded, viewed and followed:

Concept Engineering - SPEF design
Parasitic Netlist

We saw even more cool, time-saving features of the StarVision tool in action on real designs, but I’ve covered the high-level features.

Summary

Most design engineers use simulators and some formal tools, so adding a tool like StarVision Pro is going to complement your debug flow and make your debug process go much quicker, because now you can really see where all of the signals go in a design; how all of the cells, blocks and modules are connected in a hierarchy; and what comes before and after any signal in a design. Design capacity is more than adequate, with customer designs at 20B gates being run.

You can start out using StarVision Pro in GUI mode first, then start to run batch scripts for anything repetitive.

To view the recorded webinar, follow this link, or contact EDA Direct to schedule a demo of StarVision Pro to learn more.

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