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S-engine Moves up the Integration of IPs into SoCs

S-engine Moves up the Integration of IPs into SoCs
by Pawan Fangaria on 07-07-2014 at 8:30 am

As the semiconductor design community is seeing higher and higher levels of abstraction with standard IPs and other complex, customized IPs and sub-systems integrated together at the system level, sooner than later we will find SoCs to be just assemblies of numerous IPs selected off-the-self according to the design needs and specifications. Does that sound so simple? No, it’s harder than we can think of. A major burden will be on the SoC integration and verification engineers to explore optimum connectivity, find best NoC (Network-on-Chip), check every connection, debug the design, and do chip finishing by editing at the system level. And all of that has to be done within a short span of time to meet the ever shrinking time-to-market window. I am sure, focus of EDA will increase towards seamless integration of IPs into SoC; on-the-fly, correct by construction and well tested which can provide better yield.

During the 51[SUP]st[/SUP] DAC, Concept Engineeringhas introduced S-engine[SUP]TM[/SUP], a specialized schematic generation capability at system level which is a step in the right direction and at an opportune time towards IP development and SoC integration. The design houses can integrate this capability into their design tools which can allow them to visualize, debug and edit schematics at higher levels of abstraction when they are working at the top level of SoC, trying to integrate various IPs together. It’s natural that a fair amount of editing of schematics will be required at the top level while stitching the IPs together; S-engine provides that smart editing feature at the system level.

The S-engine generates schematics automatically that allows visualization at any desired level, typically the interfaces at the system level which are used to configure the IP blocks and their assembly. The smart editing at this juncture, combined with high performance and capacity allows on-the-fly management of IPs with interactive visualization, assembly and architecture design of the system, thus enabling creation of complex, high quality SoCs, NoCs and IP sub-systems. A powerful P&R technology can handle complex SoC designs of these days and produce clean schematics at the system level.

The S-engine capability from Concept provides an opportunity for EDA vendors to integrate it into their tools for such high level editing, visualization and debugging needed for system level integration. As a matter of fact, the S-engine can be easily integrated into any HLS (High Level Synthesis) tool to provide it the required control and visibility over the entire synthesis process in order to produce an optimized design at a desired level. It supports a single schematic to have components at different levels such as system, RTL, and gate, thus supporting the inherent heterogeneity in IPs from various third parties.

There are many features in S-engine which enhance its flexibility and capability to analyze and edit at different localized regions of a schematic as desired by the user. For example an IGEN symbol can have collapsible or expandable interface pins as per requirement for ease of viewing and analyzing particular buses in a schematic. Similarly there is a provision for priority routing for interface nets.

A designer can have a separate toolbar for certain selected schematic objects for ease of viewing, analyzing and editing those objects. There are native images which can be used as graphical attributes. Also, there are specific comment graphic objects that can be used for easy reference.

Since the design complexity is growing at rapid pace with multiple functions being accommodated on the same chip, enabled by multiple IPs developed separately and integrated together, it becomes evident that the IPs must be visualized, analyzed and accommodated at the system level to produce a correct and optimized SoC. This initiates the need for a capability like S-engine which can be easily integrated into EDA tools through simple and robust APIs. It provides two-way communication with the host application for cross probing, highlighting, ballooning, and other operations. The Concept proprietary algorithms enhance performance for on-the-fly schematic creation with excellent interactive editing. Interactive modification of schematic fragments is allowed for incremental schematic editing. The built-in system- and IP-level symbols enable the application to work without specific symbol libraries.

The S-engine with its appropriate API interfaces is available on multiple platforms with customizable GUI environments such as Tcl/Tk, Qt, MFC, Java SDK, Perl/Tk and wxWidgets. If you are thinking of upgrading your tools for SoC designs involving multiple IPs, it’s worth exploring S-engine and integrating it into your tools.

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