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Is there anything in VLSI layout other than pushing polygons? (2)

Is there anything in VLSI layout other than pushing polygons? (2)
by Dan Clein on 10-04-2017 at 12:00 pm

 One of the important changes that happen between 1984 and 1988 is the hardware platforms development. Calma evolved, mainframe S140 with 2 combined monitors per terminal in S280 with 2 individual monitors per terminal. This meant that from noisy and darker rooms we move to more quiet and lighted rooms. We doubled the speed and the memory in our disks. We had 2 whopping disks of 512Mb each and each was 100K US dollars.We also had 2 powerful color plotters from Versatec. Part of the layout DRC was done by hand using plots at x1000 or x10000 scale and plastic rulers. These plotters needed climate control room sat 20-21 Celsius and 40-65% humidity. A nice and refreshing room to chill when coming from a tropical day outside in Tel Aviv area. The room was also used to host the Calma mainframe and the console which we used for backups.

Even so Calma improved in speed, memory and terminals, there was no network connection between the 2 computers. You had to use tapes (!) to transfer data from S140 to S280. Later Calma tried individual workstations, but unfortunately no network between them again, you needed to write “cassette tapes” between the workstations and the mainframe. So being a layout designer meant you need know how to write & read tapes, prepare daily and weekly backups, prepare data for IBM for verifications, align plotter paper and change ink, do maintenance on computer and plotters, etc… Suddenly opportunity to expand the knowledge was there. The only thing you needed to do is volunteer.

At the same time Daisy decided to bring to market a layout tool to conquer the layout market, as they had the circuit world. As an experienced layout designer, I had the option to try it, so I volunteered. Went for a week at Daisy Corporation in Israel and got trained in ChipMaster 3.0, the crown jewel of Daisy at that time. Well, one-week training and a few weeks testing and the prognosis was bleak, they were missing important parts of the flow needed to use this software as augmentation to Calma or just replacement. Biggest flaw was that they were not capable to generate and read standard GDSII. For somebody to use this software in production this was a showstopper. So, I decided that we are not going to use them.

Guess what, I was right, Daisy had a short life afterwards. But again, was time to look for something better than Calma and the market had enough processors to just do that. Like Motorola Israel, Austin team was looking at options and 2 just showed up around 1986. CAECO a software from Silicon Compilers, a future Mentor Graphics and SDA part of future CADENCE. After a few demos and benchmarking Motorola went for CAECO as the software had circuit and layout design tools, still not linked in a network, but a least the design constraints were the same. We still used printed paper for schematics (mostly for approval controls)but in the following years we were able to open schematics and layout on the same screen. How is this for a technological revolution? What about moving from a pen to a mouse with 2 buttons. Now we had select and functions in one device, 100% time savings. This was a big jump in productivity and Motorola migrated MASKAP verification software from IBM to UNIX and we were now capable to run verification locally on each machine! Talking about productivity boost! Not only we had unlimited licenses but with local CAD we developed additional Layout Design Driven DRC verifications.

As we started standard cells, datapath cells, I/O cells, we invented specific design rules for each type of design. Onan interesting note, the first SUN machines we used were powered by 68000 processors previously designed in Austin. We progressed as the processors progressed. I am a very proud layout designer as I knew the layout project leader for 68030 Beverly Vann and worked later with the 68040 leader Geno Browning.

As we started to build new structures, we needed to build new tools. The CAD department grew to 10 Masters and PhD in software in no time and the ideas started pouring. We had to build memories (in a multi usage process –kind of SRAM) and we needed a way to automatically code the YES (1) and NO (0)in it. Our chips had firmware that had to be loaded (coded) with contacts and diffusion. From the day the base layers were ready, almost every week we had anew netlist (coding). So the last week before tapeout the firmware team will provide a final code (netlist) and we run the generator scripts and final verifications. Guess what, I volunteered there also and learnt a few more things…

The next big thing I was involved was testing of a structure called programmable logic array (PLA). This is a kind of programmable logic block used to implement combinational logic circuits. Esher Haritan was the CAD guy who had to implement the new “tool” and I volunteered to generate for him all combinational layouts to test this new “beast”. We had a lot of fun and from that date we are still friends after 30 years… I guess this was a great experience as I started to work with CAD on roadmaps for future tools.

But process technology was moving forward and we migrated to 2 layers of metal (!). Now we could have “metal directions”. As we used for local interconnect metal 1, we decided, like almost everybody in the world, to use metal 2 vertical to getoutside of the cells into busses! Well if we have 2 metals and we can plan to have some simple functions “ready” in layout we, like others invented our own standard cells (functional gates) library. At first a standard cell library was just a collection of simple gates, inverters, nands, nors, flip-flops, buffers and spare cells. We just built them on a fix height all these “gates” that were later use by all designers so the layout can be done much faster. What we did do like today, we build cell length as a multiple of the VIA to VIA spacing in metal 2 (PITCH).

We did not have modeling, or extraction of cells to use, not information about internal timing from input to output. But this was already a productivity improvement. I did cells for a few months but blocks were schematic driven and the placement and routing was manual. Tired of manual work, I started to ask around if there are tools to place and route this automatically.I heard from others that somebody in UK invented a Place & Route tool. It was called TanCell and it came from a company called Tangent. We got in touch with them and asked what is needed for a benchmark, humans versus the new software. We invited the representative to come and work inside Motorola Israel, so we had a vendor AE onsite.

After a fail start with a poor AE we got Tommy Belpasso, who was at that time their best expert. As I was the owner of the block and the library we spent 3 weeks together. The tool was crude and to make it work you had to modify libraries specifically for TOOL limitation. No more free imagination, now you had to create cells with pins in the center as the tool was the “grandfather” of channel based Place & Route. We made it but in this battle the effort was too great. What I learnt in 3 weeks was that a good AE can make a poor tool work by finding work arounds and solving on the spot issues. I was lucky to meet a few more AEs like Tommy in my later life…

One interesting development from this experiment was that we developed standard cells with the vertical metal 2 tracks included from top to bottom, at VIA to VIA pitch, but hidden as TEXT layer for M2. When we run verifications, the CAD wrote an “on the fly script” that will translate M2 Text into M2 (temporarily on GDSII creation) so we could verify at cell level that when the routing will go over, it will still be DRC clean. The lesson learnt again was that you can always get something new from another domain, in this case digital P&R and apply to improve your flow/methodology, etc. This is why volunteering to learn things not in my working duties was always appealing.

More about how a layout designer can have “spice” in their profession next time.

Dan Clein
CMOS IC Layout Concepts, Methodologies and Tools

Also read: Is there anything in VLSI layout other than “pushing polygons”? (3)

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