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Concept Engineering
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Debugging SoCs at the RTL, Gate and SPICE Netlist Levels

Debugging SoCs at the RTL, Gate and SPICE Netlist Levels
by Daniel Payne on 10-02-2019 at 10:00 am
Categories: Concept Engineering, EDA, Events

Concept Engineering - auto schematic

Debugging an IC is never much fun because of all the file formats used, the levels of hierarchy and just the sheer design size, so when an EDA tool comes around that allows me to get my debugging done quicker, then I take notice and give it a look. I was already familiar with debugging SPICE netlists using a tool called SPICEVision Pro,… Read More

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Carnegie Robotics Case Study: RTLvisionPRO

Carnegie Robotics Case Study: RTLvisionPRO
by Daniel Nenni on 09-04-2019 at 10:00 am
Categories: Concept Engineering, EDA

RTLvisionPRO has proven to be an indispensable tool which has greatly improved the productivity and work-flow of our current task: understanding, verifying, and documenting the existing RTL IP library at our company. Consisting of about 500 Verilog and VHDL files, the library has been under development for several years and… Read More

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Webinar: Designing Complex SoCs and Dealing with Multiple File Formats

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats
by Daniel Payne on 08-12-2019 at 10:00 am
Categories: Concept Engineering, EDA, Events

StarVision Pro

In SoC design it’s all about managing complexity through modeling, and the models that make up IC designs come in a wide range of file formats like:

  • Transistor-level , SPICE
  • Interconnect parasitics, SPEF
  • Gate and RTL, Verilog, VHDL

Even with standard file formats, designers still have to traverse the hierarchy to find out… Read More

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#56DAC Update – What’s New at Concept Engineering

#56DAC Update – What’s New at Concept Engineering
by Daniel Payne on 07-02-2019 at 10:00 am
Categories: Concept Engineering, EDA

Concept Engineering, DAC56

I first connected with Gerhard Angst of Concept Engineering over 15 years ago, because I was using their SpiceVision PRO tool to visual SPICE netlists received from customer designs to be debugged in a FastSPICE circuit simulator. The ability to visualize a transistor-level netlist was simply essential to quickly understanding… Read More

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Verification 3.0 Holds it First Innovation Summit

Verification 3.0 Holds it First Innovation Summit
by Randy Smith on 03-26-2019 at 5:00 am
Categories: Blue Pearl Software, Breker Systems, Concept Engineering, EDA, Events, Methodics, RISC-V, SiFive

Last week I attended the first Verification 3.0 Innovation Summit held at Levi’s Stadium in Santa Clara along with about 90 other interested engineers and former engineers (meaning marketing and sales people, like me). There was a great vibe and feel to the event as it exuded an energy level that I have not felt at an EDA event in years.… Read More

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Multi-Level Debugging Made Easy for SoC Development

Multi-Level Debugging Made Easy for SoC Development
by Pawan Fangaria on 03-01-2016 at 7:00 am
Categories: Concept Engineering, EDA

An SoC can have a collection of multiple blocks and IPs from different sources integrated together along with several other analog and digital components within a native environment. The IPs can be at different levels of abstractions; their RTL descriptions can be in different languages such as Verilog, VHDL, or SystemVerilog.… Read More

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Only One Type of OEM Seems to Work in EDA

Only One Type of OEM Seems to Work in EDA
by Paul McLellan on 08-19-2015 at 7:00 am
Categories: Concept Engineering, EDA

OEM agreements don’t seem to work in EDA. Sometimes they are signed but usually they turn out to be closer to joint marketing agreements. The reason seems to be that EDA software is complex and requires high-touch support especially when getting the product first installed and introduced into a production flow. The effect… Read More

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Starvision and SOS, a Perfect Match

Starvision and SOS, a Perfect Match
by Paul McLellan on 07-21-2015 at 7:00 am
Categories: ClioSoft, Concept Engineering, EDA

SoC design these days is largely about assembling externally developed semiconductor IP with a small amount of differentiated content. Only companies who have to adopt new processes instantly develop a lot of their own IP. It makes more sense to license it. Partially because there is not a lot of differentiation in standards-based… Read More

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Making Things Visible for 25 Years

Making Things Visible for 25 Years
by Paul McLellan on 06-03-2015 at 7:00 am
Categories: Concept Engineering, EDA

This year is most notably the 50th anniversary of Moore’s Law. It is also the 25th anniversary of Concept Engineering. They were founded in 1990 in Freiburg Germany. They started by providing automatic schematic generation from netlist. They sold primarily to other EDA companies and to internal development groups in semiconductor… Read More

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Starvision Pro: Lattice Semiconductor’s Experience

Starvision Pro: Lattice Semiconductor’s Experience
by Paul McLellan on 04-09-2015 at 7:00 am
Categories: Concept Engineering, EDA

During SNUG I took the opportunity to chat to Choon-Hoe Yeoh of Lattice Semiconductor about how they use Concept Engineering’s Starvision Pro product. He is the senior director of EDA tools and methodologies there.

Lattice Semiconductor is a manufacturer of low-power, small-footprint, low-cost programmable logic devices.… Read More