WP_Term Object
(
    [term_id] => 1012
    [name] => Concept Engineering
    [slug] => concept-engineering
    [term_group] => 0
    [term_taxonomy_id] => 1012
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 32
    [filter] => raw
    [cat_ID] => 1012
    [category_count] => 32
    [category_description] => 
    [cat_name] => Concept Engineering
    [category_nicename] => concept-engineering
    [category_parent] => 157
    [is_post] => 1
)

Expert Tool to Easily Debug RTL and Reuse in SoCs

Expert Tool to Easily Debug RTL and Reuse in SoCs
by Pawan Fangaria on 12-16-2014 at 7:00 pm

SoC design these days has become a complex and tricky phenomenon involving integration of multiple IPs and legacy RTL code which could be in different languages, sourced from various third parties across the globe. Understanding and reusing RTL code is imperative in SoC integration which needs capable tools that can accommodate large designs and provide any level of detail about any portion of the code (including its corresponding schematic, connections into the main design and so on) on-the-fly at any instant.

I was impressed after seeing a couple of demos of RTLvision PRO from Concept Engineering that shows about how the tool can help best in understanding, debugging, modifying and integrating an RTL code into an SoC.

After reading any RTL code, Verilog, VHDL or SystemVerilog, the schematic can be seen as a whole or part in cone window along with the source code. The complete source view or schematic view can be seen separately as well. The visualization and switching between the views are fast enough to traverse the whole design and understand it completely. Cross-probing between any views can be done easily and elegantly.

Any object can be selected and dropped from source to schematic, hierarchy tree to schematic or between schematic and cone window as desired. Any object in the tree can be double clicked to see multiple icons that are instantiated in the schematic. The signals can be easily traced in the schematic by double clicking at the ports in the cone and expanding the connected components. The cone windows can be used to visualize critical portions of the design and investigate into the finest levels of details.

Automatic cone extraction engine can be invoked (through dialog box by clicking on ‘Cone’ and ‘Extract Dialog’) to extract paths from any source to targets such as clocked cells or i/o ports and view them with best clarity by using available options for selective viewing. Any component in the extracted result can be double clicked to see the same in the schematic.

Identifying different clock domains, analyzing clock trees and crossings between clock domains is a key challenge for SoCs that have multiple clocks and work in various modes of operations. These must be analyzed at the RTL level and any issues with clock synchronization must be fixed there to avoid larger issues to crop up later in the design flow.

RTLvision has a versatile Clock Tree Analyzer that automatically extracts all clocks from an RTL description and provides clock tree analysis including CDC (Clock Domain Crossing) identification.

After reading the design containing multiple clock domains, the tool displays all clock trees in iconic form. By double clicking any clock tree icon, its complete clock tree structure can be loaded and displayed in a cone window. Different clock trees can be highlighted in different colors to improve visibility and analysis. In the schematic, the number of flops count in a module (at any level) connected to a clock feeding that module is displayed along with the clock connection which lets designers to verify the clock and flops with each module without getting into the cumbersome task of looking at each individual flop and clock.

The Clock Tree Analyzer displays CDC between each clock domain with thick and thin lines depicting the connection strength (determined by the number of connections) between them. The clock domains and their respective flops in schematic can be displayed in different colors. There are multiple options to arrange flops with different contexts for better viewing and easy analysis.

An integrated Waveform Viewer compiles VCD simulation data into its own high-speed format for accelerated waveform viewing and analysis. The signals can be interactively traced between source code, schematic and waveform window.

RTLvision also provides automated documentation of new, changed or reused RTL code which can be Verilog/VHDL schematic, PDF file, postscript output or bitmap image. Also, TCL based UserWare APIs are provided to extend RTLvision functionality according to the specific needs of any organization and interfacing with other tools.

Look at the demos RTLvision basic features and Clock Tree Analyzer at Concept Engineering website to know more details. Contact info@concept.de or sales@edadirect.com for any more specific information you may need.

More Articles by PawanFangaria…..