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Parasitic Debugging in Complex Design – How Easy?

Parasitic Debugging in Complex Design – How Easy?
by Pawan Fangaria on 01-23-2014 at 9:00 am

When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitances. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex it would be to debug that design at parasitic level. We definitely need smart tools to be able to analyse different parts of a design, at different levels of hierarchy, and at different levels of abstraction such as transistor, gate and RTL.

Good news is that we do have such tools available from Concept Engineeringwhich enable designers to do very fast design exploration, visualize the design at different levels, reduce complexity, and thus debug the design easily, precisely and in lesser time. I was delighted to go through a webinarhighlighting parasitic debugging by using StarVision and SpiceVision. The webinar included a demo as well, conducted very nicely by Lokesh Akkipeddi at Eda Direct. Lokesh demonstrated features with live menus which help locate the exact problem area with great navigation and cross-probing, simplify portion of the design view at a desired level (e.g. modify symbols, move up to gate or down to transistor level, remove RC etc.) to understand the problem, review Spice netlist and fix at any level as appropriate.

The design can be visualized at various levels such as transistor, gate or RTL and those can be mixed with each other as required. Parasitic for different wires can be viewed in different colors for easy correlation. Similarly the source code can be viewed for any module or component of the design.

Industry leading Spice and post-layout interfaces (including those from EDA majors like Synopsys, Cadenceand Mentor) are supported which StarVision can read and also write out Spice netlist. Schematic can be exported to Cadence Virtuoso through SKILL.

During the demo, I could see a good level of navigation moving through different levels of hierarchies connected through nets, signal distribution, looking inside a module or individual pin, and provision to hide unconnected pins to remove clutter and many other features.

Cone extraction is a special feature which caught my attention. It can expose all inputs connected to a pin as well as all outputs from it to probe with closer vision.

[Circuit with RC and without RC; Parallel transistors merged to recognize gates]

Similarly, to view a circuit in simple form, there is an interesting feature to reduce netlist where RC can be filtered out from a circuit to view it in simple form of transistors. Also, parallel transistors can be merged to easily recognize CMOS gates. Large resistances and capacitances can be recognized, viewed and values observed, if that asks for any modification in the circuit.

Then there is cross-probing up to the source level and the code can be highlighted in the same color as selected for the particular component.

Spice code can be written for any desired portion of the circuit and that can be used for external partial simulation for analysis and decision making.

An excellent extensible feature is that APIs can be developed for customized functionality at any level (Spice, gate or RTL) by using tcl scripts. Over 100 example APIs have been developed; some of those are shown in the table.

I can go on and on to mention more features and still not be able to justify the real essence of those through these pictures. It would really help designers to gain the gist of those excellent features by seeing the live presentation and demo in the webinar. Go for it!!

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