WP_Term Object
(
    [term_id] => 1012
    [name] => Concept Engineering
    [slug] => concept-engineering
    [term_group] => 0
    [term_taxonomy_id] => 1012
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 35
    [filter] => raw
    [cat_ID] => 1012
    [category_count] => 35
    [category_description] => 
    [cat_name] => Concept Engineering
    [category_nicename] => concept-engineering
    [category_parent] => 157
    [is_post] => 1
)

Expert Tool to View and Debug Design Issues at Spice Level

Expert Tool to View and Debug Design Issues at Spice Level
by Pawan Fangaria on 09-12-2014 at 7:00 am

Spice view of a design, block or fragment of the design is probably the lowest level of functional description of a circuit in terms of transistors, resistors, capacitors, interconnect and so on, which in several ways acts as an ultimate proof of pudding for any semiconductor design before manufacturing. However, it’s generally very clumsy and difficult, unless one is an expert Spice level engineer, to read and understand a design description (which may be a basic library cell) written in Spice. Not to mention, Spice levels circuits (which could be in the form of library cells) are integral part of digital, analog, mixed-signal, PCB and even MEMS designs. And it’s not possible to have large designs directly in Spice format; that’s the reason often a need arises to look at a small portion of design in Spice format. What if we have an automatic tool which can generate circuit schematic on-the-fly at any desired level of hierarchy, show multiple views in different windows including Spice source code to cross probe among them and several other features for easy debugging of a design at Spice level? I guess that will be an ultimate in getting us closer to that proof of pudding.

Although I have talked about several capabilities of Concept Engineeringaiding into SoC design, debug and verification, I realized the real value of SpiceVision PRO when I looked at its capabilities in detail and also watched a quick demo videodedicated to SpiceVision. It’s a must see to appreciate the real power of the tool.

SpiceVision provides a graphical Spice netlist viewer and analyzer for pre-layout as well as post-layout Spice including parasitic netlist in SPEF, DSPF or RSPF format. It supports 32-bit as well as 64-bit database to accommodate large SoCs. It also provides Tcl based userware API interface which can be used for advanced customization and electrical rule checks (ERC). The interface allows access to the internal database and GUI, through which users can analyze the design data and generate specific reports and design checks as desired. Selected fragments of circuit and critical paths can be easily and clearly displayed through a Cone Window feature. A circuit fragment can also be saved as a separate Spice file which can be simulated and debugged later. There is provision to export schematics into CadenceVirtuoso Schematic Editor Environment.

The design can be viewed at all possible hierarchy levels from top level to all sub-circuit levels. The hierarchy tree, source code and schematic diagram are displayed in different adjacent windows. A search engine can be used to generate a list of interest entities from which the designer can select any portion to generate the circuit diagram.

Any selected fragment or critical path can be displayed in magnified form in a Cone Window and details (such as R, C, and transistors) viewed and analyzed. The fragmented portion of the circuit can be exported as Spice netlist for partial simulation which can run 10 to 100 times faster compared to full circuit simulation.

At times, when a circuit become too much cluttered due to detailed display of parasitics, it becomes very difficult to recognize the actual circuit. SpiceVision has a feature where parasitics such as parallel capacitors can be merged to simplify the circuit. Also, the circuit can be displayed with just transistors or gates without parasitics, thus enabling designers for further design navigation and exploration.

As a final validation of the circuit, the layout at the final stage is extracted for verification which generates very large and complex SPEF and DSPF netlists with multiple critical paths. These critical paths can be displayed, analyzed and saved for critical path simulation. SpiceVision eases post-layout debugging significantly.

The specific part of a design saved in separate Spice file can also be used as IP in other designs. The symbols of components such as resistors, capacitors, transistors, current/voltage sources etc. are used as standard symbols, however they can easily link to external symbol libraries.

To get more information on this product, obtain the datasheet here.

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