SIC 2020 Forum 800x100 1
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3211
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3211
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
)

Transceiver Verification of a 20nm Altera FPGA Device

Transceiver Verification of a 20nm Altera FPGA Device
by Daniel Payne on 09-11-2014 at 6:00 pm

FPGA devices are a great way to drive silicon technology development because they contain both digital and analog IP, along with sophisticated IO cells. The highest performance IOs are transceivers, and Altera has recently designed the Arria 10 device family to include up to 96 transceivers, using a 20nm technology that can achieve data rates up to 28.1 Gbps. Users just know that there is a transmit and receive pair, however inside of the FPGA there are complex building blocks to sustain these data rates:


Arria 10 FPGA Transceiver Block Diagram

These transceiver cells are really analog IP that require transistor-level circuit verification and validation to work across:

  • Process corners
  • Operating voltages
  • Temperature ranges

Multiple clock sources are used in the transceiver block diagram, one of them is called fPLL, or Fractional-N Phase Locked Loop, and it provides both integer and fractional frequency clocks, with a range of data rates from 611 Mbps to 12.5 Gbps.


Fractional-N PLL

A traditional SPICE circuit simulator could be used to verify the proper operation of this sensitive design, however you would likely have to wait days to get results with a dynamic range greater than 100dB. To get simulation results faster you might even be tempted to use a FastSPICE simulator, however the results wouldn’t be accurate enough. Fortunately, there’s a happy medium between using a SPICE and FastSPICE circuit simulator, and that is using an Analog FastSPICEtool instead. Engineers at Berkeley Design Automation(now owned by Mentor Graphics) created this product category several years ago, and it has found a growing place in the family of transistor-level simulators where speed and analog accuracy are required.Related: Analog FastSPICE Update at DAC

Mentor has nicknamed their Analog FastSPICE tool AFS, and at Altera they were able to use AFS on transceiver simulations with up to 16M elements, which included post-layout netlists. Eye diagrams are a common analysis method to evaluate how clearly a sequence of 1-0 can be sent or received.


Transceiver Eye Diagram

At the 20nm node, a more rigorous validation and characterization flow was specified at Altera to include five metrics:

  • Systematic verification under all conditions, well-defined pass/fail criteria.
  • Automated regressions for pre-layout and post-layout netlists.
  • Ensure a common design environment and simulation conditions, consistency.
  • Uncover any statistical failing corners prior to tape-out.
  • Track all validation progress.

Within the Mentor EDA tools there’s something called the Analog Characterization Environment(ACE), and this was used to ensure that the five metrics listed above were actually adhered to and accomplished. Some 250 tests were defined in this validation suite, and there were over 6,000 simulations run, including Monte Carlo.Related: Analog FastSPICE AMS — Simple, Fast, nm-Accurate Mixed-Signal Verification

With this flow you can look at statistical results to help make design decisions. The probability of each iteration is displayed in chart format with Percentage on the Y-Axis and parameter (foundry process variation) on the X-Axis:


Voltage Regulator Monte Carlo Distribution

The statistical results on the voltage regulator show that the design is not centered yet between the two red line values of 1.09 and 1.11, so tweaking the transistor sizes is required for this design to be centered for maximum yield.

Two more Monte Carlo simulation results uncovered circuits that required more tuning to meet specifications:


Rx AC Peaking Monte Carlo Results


DC Offset Results for the Secure Digital block

With over 6,000 circuit simulations used in this characterization and verification flow, accurate results were delivered in a timely fashion by using AFS technology, like:

  • Multithreading
  • Multi-core parallel
  • Distributed multi-core parallel

Many of these runs could be automatically distributed across cores in a single machine, and across multiple machines. Managers and designers could look at the progress of verification across all the characterization variations.

Summary

20nm design is demanding, requiring a massive amount of circuit simulation to characterize and verify across: corners, sweeps, Monte Carlo and nests. Altera was successful in using Mentor tools like AFS and ACE in the design of their 20nm transceivers for the Arria 10 family.

There’s a six page white paper on this topic, ready for download after a brief registration step at Mentor’s web site.


Comments

0 Replies to “Transceiver Verification of a 20nm Altera FPGA Device”

You must register or log in to view/post comments.