Aniah and Electrical Rule Checking (ERC) #61DAC

Aniah and Electrical Rule Checking (ERC) #61DAC
by Daniel Payne on 08-06-2024 at 10:00 am

Aniah #61DAC min

Visiting a new EDA vendor at #61DAC is always a treat, because much innovation comes from the start-up companies, instead of the established big four EDA companies. I met with Vincent Bligny, Founder and CEO of Aniah on Wednesday in their booth, to hear about what they are doing differently in EDA. Mr. Bligny has a background working… Read More


Webinar: Electrical Rules Checking – How to Reduce Thousands of False Errors in 15 Minutes Using OneCheck Smart Clustering

Webinar: Electrical Rules Checking – How to Reduce Thousands of False Errors in 15 Minutes Using OneCheck Smart Clustering
by Admin on 06-03-2024 at 8:48 pm

Analyzing electrical errors across an IP or a SoC at top level, can be a painful and long process, often requiring extensive setup time and hundred of hours to distinguish real issues from false positives.

To address this challenge, Aniah developed OneCheck, a formal analysis tool capable of detecting 100% of electrical errors… Read More


Electrical Rule Checking and Exhaustive Classification of Errors

Electrical Rule Checking and Exhaustive Classification of Errors
by Daniel Payne on 04-16-2024 at 10:00 am

Aniah tool flow min

The goal of SoC design teams is to tape-out their project and receive working silicon on the first try, without discovering any bugs in silicon. To achieve this lofty goal requires all types of specialized checking and verification during the design phase to prevent bugs. There are checks at the system level, RTL level, gate level,… Read More


Soft checks are needed during Electrical Rule Checking of IC layouts

Soft checks are needed during Electrical Rule Checking of IC layouts
by Daniel Payne on 02-28-2024 at 10:00 am

Metal1 Via Metal2 s

IC designs have physical verification applications like Layout Versus Schematic (LVS) at the transistor-level to ensure that layout and schematics are equivalent, in addition there’s an Electrical Rules Check (ERC) for connections to well regions called a soft check. The  connections to all the devices needs to have the most… Read More


Multi-Level Debugging Made Easy for SoC Development

Multi-Level Debugging Made Easy for SoC Development
by Pawan Fangaria on 03-01-2016 at 7:00 am

An SoC can have a collection of multiple blocks and IPs from different sources integrated together along with several other analog and digital components within a native environment. The IPs can be at different levels of abstractions; their RTL descriptions can be in different languages such as Verilog, VHDL, or SystemVerilog.… Read More


Growing Innovation in Modern PCB Design Tools

Growing Innovation in Modern PCB Design Tools
by Pawan Fangaria on 04-26-2015 at 7:00 am

In last 30+ years, the electronic design industry has seen rapid changes more than any other industry. The change has taken place in the whole electronic ecosystem including semiconductor technology, transistor design, IC / SoC design, PCB, and system design. Today, a PCB can be very complex connecting several heterogeneous… Read More


A Comprehensive Power Optimization Solution

A Comprehensive Power Optimization Solution
by Pawan Fangaria on 04-20-2015 at 7:00 am

In an electronic world driven by smaller devices packed with larger functions, power becomes a critical factor to manage. With power consumption leading to heat dissipation issues, reliability of the device can be affected, if not controlled or the device not cooled. Moreover, for mobile devices such as smartphones or tablets… Read More


StarVision to Debug and Analyze Designs at All Levels

StarVision to Debug and Analyze Designs at All Levels
by Pawan Fangaria on 10-09-2014 at 4:00 pm

In today’s SoC world where multiple analog and digital blocks along with IPs at different levels of abstractions are placed together on a single chip, debugging at all levels becomes quite difficult and clumsy. While one is working at the top level and needs to investigate a particular connection at an intermediate hierarchical… Read More


Expert Tool to View and Debug Design Issues at Spice Level

Expert Tool to View and Debug Design Issues at Spice Level
by Pawan Fangaria on 09-12-2014 at 7:00 am

Spice view of a design, block or fragment of the design is probably the lowest level of functional description of a circuit in terms of transistors, resistors, capacitors, interconnect and so on, which in several ways acts as an ultimate proof of pudding for any semiconductor design before manufacturing. However, it’s generally… Read More


Concept Engineering Showcases Effective SoC Debugging Techniques

Concept Engineering Showcases Effective SoC Debugging Techniques
by Pawan Fangaria on 05-15-2014 at 10:00 pm

In a complex environment of semiconductor design where an SoC can have several millions of gates and multiple number of IPs at different levels of abstractions from different sources integrated together, it becomes really difficult to understand and debug the overall SoC design. Of course, along with the SoC integration, optimization… Read More