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September 11, 2019September 17, 2019

Tcling Your Way to Low Power Verification

Tcling Your Way to Low Power Verification
by Bernard Murphy on 09-11-2019 at 5:00 am
Categories: EDA, Mentor, a Siemens Business

OK – maybe that sounds a little weird, but it’s not a bad description of what Mentor suggests in a recent white-paper. There are at least three aspects to power verification – static verification of the UPF and the UPF against the RTL, formal verification of state transition logic, and dynamic verification of at least some critical… Read More

April 19, 2016

A Versatile Design Platform with Multi-Language APIs

A Versatile Design Platform with Multi-Language APIs
by Pawan Fangaria on 04-19-2016 at 7:00 am
Categories: Defacto Technologies, EDA

In one of my whitepapers “SoCs in New Context – Look beyond PPA”, I had mentioned about several considerations which have become very important in addition to power, performance, and area (PPA) of an SoC. This whitepaper was also posted in parts as blogs on Semiwiki (links are mentioned below). Two important… Read More

July 5, 2015

Cellphones on the Path of Extinction

Cellphones on the Path of Extinction
by Pawan Fangaria on 07-05-2015 at 4:00 am
Categories: General, Mobile

Semiconductor based electronics has continuously improved lives of people through various kinds of technology upgrades in the gadgets for our daily use. Imagine the journey from a mechanical typewriter to a laptop computer connected through a laser printer, transition from black & white photography to exotic coloured… Read More

December 21, 2014June 14, 2019

Ensuring Safety Distinctive Design & Verification

Ensuring Safety Distinctive Design & Verification
by Pawan Fangaria on 12-21-2014 at 12:00 pm
Categories: Cadence, EDA

In today’s world where every device functions intelligently, it automatically becomes active on any kind of stimulus. The problem with such intelligence is that it can function unfavorably on any kind of bad stimulus. As the devices are complex enough in the form of SoCs (which at advanced process nodes are more susceptible to … Read More

December 16, 2014June 14, 2019

Expert Tool to Easily Debug RTL and Reuse in SoCs

Expert Tool to Easily Debug RTL and Reuse in SoCs
by Pawan Fangaria on 12-16-2014 at 7:00 pm
Categories: Concept Engineering, EDA

SoC design these days has become a complex and tricky phenomenon involving integration of multiple IPs and legacy RTL code which could be in different languages, sourced from various third parties across the globe. Understanding and reusing RTL code is imperative in SoC integration which needs capable tools that can accommodate… Read More

September 12, 2014June 14, 2019

Expert Tool to View and Debug Design Issues at Spice Level

Expert Tool to View and Debug Design Issues at Spice Level
by Pawan Fangaria on 09-12-2014 at 7:00 am
Categories: Concept Engineering, EDA

Spice view of a design, block or fragment of the design is probably the lowest level of functional description of a circuit in terms of transistors, resistors, capacitors, interconnect and so on, which in several ways acts as an ultimate proof of pudding for any semiconductor design before manufacturing. However, it’s generally… Read More

August 22, 2014

Automatic RTL Restructuring: A Need Rather Than Convenience

Automatic RTL Restructuring: A Need Rather Than Convenience
by Pawan Fangaria on 08-22-2014 at 5:00 pm
Categories: EDA

In the semiconductor design industry, most of the designs are created and optimized at the RTL level, mainly through home grown scripts or manual methods. As there can be several iterations in optimizing the hierarchy for physical implementation, it’s too late to do the hierarchical optimizations after reaching the floor plan… Read More

August 21, 2014June 14, 2019

Crossfire – Your partner for IP development, what’s new?

Crossfire – Your partner for IP development, what’s new?
by Pawan Fangaria on 08-21-2014 at 4:00 pm
Categories: EDA, Fractal Technologies

As the SoCs and IPs grow in sizes and complexities, the number of formats, databases, libraries of standard cells and IOs also increase. It becomes a clumsy task to check every cell in a library, its consistency among various format with respect to functionality, timing, naming, labels and so on, and its complex physical properties… Read More

August 2, 2014June 14, 2019

Enabling Higher Level Design Automation with Smart Tools

Enabling Higher Level Design Automation with Smart Tools
by Pawan Fangaria on 08-02-2014 at 10:00 pm
Categories: Concept Engineering, EDA

Although design houses have always strived for optimizing best design flows according to their design needs by customizing the flows using effective and efficient internal as well as external tools, this need has further grown in the context of design scenarios getting wider and wider from transistor, gate and RTL to system level.… Read More

May 6, 2014June 14, 2019

Flexible Integration System for IPs into SoC

Flexible Integration System for IPs into SoC
by Pawan Fangaria on 05-06-2014 at 7:30 am
Categories: Dassault Systemes, EDA

The number of IPs with growing complexity and heterogeneity is ever increasing (counting into hundreds) to be integrated into a single SoC. It’s not possible to have them all available at once and in a single repository for the integration engineers to assemble all of them together and integrate into the SoC. The reality is that … Read More

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Taiwan ESD Workshop Recording Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction Finding Your Way Through Verification (Text) Concerned about IP security threats for your SoCs? REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [category_96] => 1 [category_6435] => 1 [category_95] => 1 [category_157] => 1 [category_50] => 1 [category_13] => 1 [category_90] => 1 [category_89] => 1 [category_3611] => 1 [category_178] => 1 [category_14418] => 1 [category_51] => 1 [category_97] => 1 [cpt_page] => 1 [others_blog_page] => 1 [category_44] => 1 [category_5] => 1 [category_32] => 1 [category_22] => 1 ) [display_widget_mobile] => 1 )

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Tag: tcl

Tcling Your Way to Low Power Verification

A Versatile Design Platform with Multi-Language APIs

Cellphones on the Path of Extinction

Ensuring Safety Distinctive Design & Verification

Expert Tool to Easily Debug RTL and Reuse in SoCs

Expert Tool to View and Debug Design Issues at Spice Level

Automatic RTL Restructuring: A Need Rather Than Convenience

Crossfire – Your partner for IP development, what’s new?

Enabling Higher Level Design Automation with Smart Tools

Flexible Integration System for IPs into SoC

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MUGM 2019 – MunEDA User Group...

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Recent Forum Threads

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World's First Tech Ambassador

Physical Design Engineers @ Apple, Munich, Germany

Graphics Systems Verification Engineer @ Apple, UK

GPU Modelling Engineers @ Apple, UK