Ten Innovative Debugging Techniques – Pre & Post Layout

Ten Innovative Debugging Techniques – Pre & Post Layout
by Pawan Fangaria on 04-21-2014 at 8:00 pm

In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle… Read More


Parasitic Debugging in Complex Design – How Easy?

Parasitic Debugging in Complex Design – How Easy?
by Pawan Fangaria on 01-23-2014 at 9:00 am

When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitances. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex… Read More


What Makes A Designer’s Day? A Bottleneck Solved!

What Makes A Designer’s Day? A Bottleneck Solved!
by Pawan Fangaria on 12-04-2013 at 3:00 pm

In an environment of SoCs with tough targets of multiple functionalities, smallest size, lowest power and fastest performance to achieve within a limited design cycle window in order to meet the rigid time-to-market requirements, any day spent without success becomes very frustrating for a designer. Especially during tape-out… Read More