In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle has to go hand-in-hand along with the design and verification; the architect of the design should be able to make expert judgement and take appropriate action before a small weakness in the design can get amplified further down the design cycle. In such a scenario with high complexity, size and density of a semiconductor design, there is nothing like having tools which can help designers debug the design by visually showing them the portions of design, their interconnections and interfaces, associated code and results, and so on at any stage of the design and at the level of granularity they desire.
I admire such set of tools equipped with very practical and useful capabilities and offered in a comprehensive integrated platform by Concept Engineering. It’s an opportunity to learn about the capabilities of these tools and how they can be leveraged through specific techniques to effectively debug large SoCs at pre-layout as well as post-layout stages through a free webinaron 29[SUP]th[/SUP] April, hosted by EDA Direct. It must be noted that more than 75% of top 20 semiconductor design houses are gaining significant benefits in their design productivity by using these tools and have exercised them through some of the largest semiconductor designs in the industry. The tools are versatile enough supporting most of the industry standard formats that include Verilog, SV, VHDL, EDIF, Spice, HSpice, Spectre, Calibre, CDL, DSPF, RSPF, SPEF, Eldo, PSpice and IBIS.
So, what are the debugging techniques to learn from this webinar? Check the summarised list below which will entice you to sign-up for this webinar.
1. Render schematics on the fly for RTL, Gate or Spice level netlists to understand circuit functions in easiest and simplistic manner.
2. Extract, navigate and save fragments of circuits as Spice netlists with the ‘cone view’, for re-use as IP or external use in partial simulation.
3. Drag & drop selected elements between all design views (schematic, cone, parasitic and source code view) to cross probe and shorten debug time, especially during tape-out for full-chip debug.
4. Automatically create digital logic symbols and schematics from pure Spice netlists for easy design exploration.
5. Visualize and analyze post layout parasitic networks (in DSPF, RSPF or SPEF format) and create Spice netlists for critical path simulation and analysis.
6. Recognize CMOS functions easily by instantly turning off parasitic structures in Spice circuits to remove the clutter around transistor symbols.
7. Export schematics or their fragments into CadenceVSE (Virtuoso Schematic Editor) for further optimization and debugging.
8. Perform ERCchecking by verifying and debugging connectivity; identify floating input or output nets, heavily connected nets etc. especially in multi fan-in and fan-out structures.
9. Generate easily comprehensible design statistics and reports.
10. Extend the functionality of SpiceVision to match specific project needs by interfacing with the open database through tcl scripts.
There are many other features in these tools beyond the ones listed above; for example, clock tree analysis, timing back-annotation, integrated waveform viewing etc. One can see through a circuit what she wants to see. The clean handling and performance of each operation in the tools is remarkable. One can tell only after watching it.
It’s worth attending this webinar to know and appreciate about the actual capabilities of these set of tools working at transistor, gate and RTL level with all kinds of design views and at mixed-signal and mixed-language level.
Register herefor a one hour session on 29[SUP]th[/SUP] April at 10 AM PDT.
Contact firstname.lastname@example.org for any more information you may require.