My first job out of college was doing transistor-level circuit design, so I’m always curious about how companies are doing billion-transistor chip design and debug these days at the FPGA companies.
I spoke with Yaron Kretchmer,he works at Altera and manages the engineering infrastructure group where they have a compute farm, manage EDA licenses and create tool flows. Yaron has been at Altera for 10 years, has a background in ASIC (LSI Logic) and full-custom IC design.
Yaron Kretchmer, Altera
Q: How do you debug these billion-transistor FPGAs during design and testing?
A: We’ve taken a graphical approach using tools from Concept Engineering.
Q: Why use a graphical debug approach?
A: While I was at LSI Logic 16 years ago we first adopted a graphical debug approach, and we integrated Widgets from Concept Engineering into our internal CAD tools. This allowed our design engineers to quickly visualize their netlist for debugging.
Q: What other EDA companies have embedded these Widgets into their tools?
A: Several: Synopsys, Atrenta, Xilinx all use the Widgets.
Q: Concept Engineering is a German company, so how do you get support when they are so many time zones away?
A: Support from Concept Engineering has been great, our local AE support comes from EDA direct. The tools have been stable and well documented, so it really reduces the need for factory support.
Q: At LSI Logic, did you only visualize at the Gate level?
A: In the beginning we used the gate-level tool, then moved up to using the RTL tool next.
Q: How is debug different at Altera?
A: Here at Altera we are using a combination of all three levels: RTL, Gate and Transistor. We asked Concept Engineering to combine the three separate tools into a single tool, now called StarVision Pro, so that we could more easily debug our billion transistor chips.
Stratix IV FPGA, die photo
Q: What is a typical debug task that you face?
A: The most common use case is to trace through a design because there’s a functional problem that we need to debug, so with this visual approach we can quickly traverse the design hierarchy. It scales well for very large designs, so with 5 billion transistors in an FPGA using a mix of RTL, gate-level and SPICE-level descriptions we can load our designs, and traverse the entire design in one tool.
We see a functional bug, then load our design, traverse it with StarVision Pro in a hierarchical fashion.
Q: Who is doing this visual debug at Altera?
A: Our users are design engineers, even some test and product engineers are using the tool. Design engineers use this for debugging a new family of devices. Test engineers also use this during test development and silicon debug.
Q: Would FPGA users need to debug visually?
A: Yes, the end users of FPGA can visualize at the RTL and some gate-level during their debug process.
Q: At Altera which OS is used?
A: We use both Windows and Linux boxes. The test group uses more of a Windows environment, while our design engineers are mostly Linux users.
Q: How many engineers are using this visual debug approach?
A: We have dozens of engineers using StarVision for debug. We even use StarVision for automated quality control checking related to our data management system, which is used by hundreds of engineers.
Q: How much time is spent in visual debugging?
A: The usage depends on the type of problem they are solving. For design debugging it could be hours per session. For automated checking the usage is 20 seconds or less.
Q: How do you write your automated checks?
A: It is a script-friendly tool using a Tcl API.
Altera designs a wide array of FPGA devices with a capacity in the billion-transistor range, and they have been using a visual debug approach with tools from Concept Engineering.
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