WP_Term Object
(
    [term_id] => 1012
    [name] => Concept Engineering
    [slug] => concept-engineering
    [term_group] => 0
    [term_taxonomy_id] => 1012
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 34
    [filter] => raw
    [cat_ID] => 1012
    [category_count] => 34
    [category_description] => 
    [cat_name] => Concept Engineering
    [category_nicename] => concept-engineering
    [category_parent] => 157
    [is_post] => 1
)

StarVision to Debug and Analyze Designs at All Levels

StarVision to Debug and Analyze Designs at All Levels
by Pawan Fangaria on 10-09-2014 at 4:00 pm

In today’s SoC world where multiple analog and digital blocks along with IPs at different levels of abstractions are placed together on a single chip, debugging at all levels becomes quite difficult and clumsy. While one is working at the top level and needs to investigate a particular connection at an intermediate hierarchical level, she has to pass through several steps. Similarly one has to go through specified procedures when merging blocks at different levels of abstraction in a design. What if we have an automated tool which provides an integrated environment for all levels (e.g. RTL, Gate and Transistor) in mixed-signal designs in a single cockpit which can also be customized according to designers’ need? It will significantly improve designers’ productivity in integrating, analyzing and debugging SoC designs.

Yesterday, I came across a five minutes video demoon Concept Engineering’sStarVision tool posted on EDA Directwebsite. Although I have signed-up for Concept’s upcoming webinar on 21[SUP]st[/SUP] Oct, I just dived down this video. It was awesome in introducing the integration and navigation part of StarVision with a real example on how an RTL or a Spice level block can be merged into a design while staying in the same GUI and then stepping through several levels of hierarchy, views, cross probing etc. I could easily visualize how easy it would be for designers to analyze and debug the design using this environment.

This is an example of an IP; the top level is in Verilog with three instances – CPU, SYS and Parity. On the right side is the image of the CPU block which is loaded into the design. Any level of hierarchy inside the CPU block can be easily descended and probed against its code in Verilog.

Driving down the CPU block one can see the content coming from Verilog netlist. Above is the image of a multiplier instance inside the CPU. Its Verilog code view can be opened and probed against the schematic. The probing can be done from both sides.

Now let’s say SYS block which is at RTL level in Verilog has to be loaded and merged with the design.

The above picture shows the Verilog merge option and the top level view after SYS block loaded. The SYS block can again be navigated through for viewing and analyzing its contents down the whole hierarchy.

The Parity block is at transistor netlist level and has the Spice code view. This block is also loaded through hspice merge option as shown above. The demo shows driving down this block as well and cross probing between transistor level schematic and Spice netlist at any point in the hierarchy.

Cone window is an excellent feature through which any signal can be picked from the schematic at any level and clicked through to load objects connected to it. One can navigate through multiple levels of hierarchy at the same time staying in the same GUI and display all the different levels of inputs in the same view.

This is just a small demo which shows loading and navigating through different views of the design. There are host of other important features which makes a designer’s life easy in debugging complex SoC and IC design in complete transparent manner. To mention a few of them are – extraction of circuit fragments and saving as Spice netlists for investigation and re-use, easy design exploration by symbol creation from Spice netlists, dragging & dropping of selected components between all design views, analysis of parasitic networks and creation of Spice netlist for critical path simulation, ERC checking, and many more.

EDA Direct is organizing a free webinar which will provide complete details about Concept Engineering’s StarVision[SUP]TM[/SUP] PROcapabilities along with its usage of in-built utilities to provide a versatile environment for easily analyzing, debugging and integrating SoCs and ICs. The webinar’s schedule is as follows –

Date: 21 October, 2014
Time: 10:00 AM – 11:00 AM PDT
Media: Online via WebEx

Register here to reserve your attendance.

Today, 16 out of top 20 semiconductor companies are using Concept Engineering visual debugging technologies. It will be worth spending one hour to know about actual details of this debugging environment.

Contact info@concept.de and sales@edadirect.com for any more information.

More Articles by PawanFangaria…..