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What are you ready to mobilize for FPGA debug?

What are you ready to mobilize for FPGA debug?
by Frederic Leens on 12-04-2017 at 7:00 am
Categories: EDA, FPGA

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There are 3 common misconceptions about debugging FPGA with the real hardware:

[LIST=1]

  • Debugging happens because the engineers are incompetent.
  • FPGA debugging on hardware ‘wastes’ resources.
  • A single methodology should solve ALL the problems.
    • … Read More
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    Optimizing Prototype Debug

    Optimizing Prototype Debug
    by Bernard Murphy on 11-09-2016 at 7:00 am
    Categories: EDA, Mentor, a Siemens Business

    In the spectrum of functional verification platforms – software-based simulation, emulation and FPGA-based Image Removedprototyping – it is generally agreed that while speed shoots up by orders of magnitude (going left to right) ease of debug drops as performance rises and setup time increases rapidly, from close to nothing… Read More

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    Getting out of DIY mode for virtual prototypes

    Getting out of DIY mode for virtual prototypes
    by Don Dingee on 09-26-2016 at 4:00 pm
    Categories: Automotive, EDA, IoT, Synopsys

    Virtual prototyping has, inexplicably, been largely a DIY thing so far. Tools and models have come from different sources with different approaches, and it has been up to the software development team to do the integration step and cobble together a toolchain and methodology that fits with their development effort.

    That integration… Read More

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    A New Player in the Functional Verification Space

    A New Player in the Functional Verification Space
    by Bernard Murphy on 08-22-2016 at 7:00 am
    Categories: Consensia, EDA

    Israel has a strong pedigree in functional verification. Among others, Verisity (an early contributor to class-based Image Removedtestbench design and constrained random testing) started in Israel and RocketTick (hardware-based simulation acceleration), acquired more recently by Cadence, is based in Israel. So when … Read More

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    Learn How to Debug UVM Test Benches Faster – Upcoming Synopsys Webinar

    Learn How to Debug UVM Test Benches Faster – Upcoming Synopsys Webinar
    by Bernard Murphy on 07-14-2016 at 4:00 pm
    Categories: EDA, Synopsys

    UVM for developing testbenches is a wonderful thing, as most verification engineers will attest. It provides Image Removedabstraction capabilities, it encapsulates powerful operations, it simplifies and unifies constrained-random testing – it has really revolutionized the way we verify at the block and subsystem level.… Read More

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    Bringing Formal Verification into Mainstream

    Bringing Formal Verification into Mainstream
    by Pawan Fangaria on 04-28-2016 at 7:00 am
    Categories: EDA, Synopsys

    Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More

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    Mentor at DVCon – Visualize This

    Mentor at DVCon – Visualize This
    by Bernard Murphy on 03-10-2016 at 12:00 pm
    Categories: EDA, Mentor, a Siemens Business

    Steve Bailey entertained us during lunch on Tuesday with a talk on debug and visualization in the Mentor Image Removedplatform. Steve is based in Colorado, so had to spend the first part of his talk gloating about their Super Bowl win, but I guess he deserves that.

    On a more technical note, he showed us a familiar survey they had completed… Read More

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    Multi-Level Debugging Made Easy for SoC Development

    Multi-Level Debugging Made Easy for SoC Development
    by Pawan Fangaria on 03-01-2016 at 7:00 am
    Categories: Concept Engineering, EDA

    An SoC can have a collection of multiple blocks and IPs from different sources integrated together along with several other analog and digital components within a native environment. The IPs can be at different levels of abstractions; their RTL descriptions can be in different languages such as Verilog, VHDL, or SystemVerilog.… Read More

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    Fastest SoC time-to-success: emulators, or FPGA-based prototypes?

    Fastest SoC time-to-success: emulators, or FPGA-based prototypes?
    by Don Dingee on 02-11-2016 at 12:00 pm
    Categories: EDA, FPGA, S2C Prodigy

    Hardware emulators and FPGA-based prototyping systems are descendants of the same ancestor. The Quickturn Systems Rapid Prototype Machine (RPM) introduced in May 1988 brought an array of Xilinx XC3090 FPGAs to emulate designs with hundreds of thousands of gates. From there, hardware emulators and FPGA-based prototyping … Read More

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    Michael Sanie Plays the Synopsys Verification Variations

    Michael Sanie Plays the Synopsys Verification Variations
    by Paul McLellan on 08-31-2015 at 7:00 am
    Categories: EDA, Synopsys

    Image RemovedI met Michael Sanie last week. He is in charge of verification marketing at Synopsys. I know him well since he worked for me at both VLSI Technology and Cadence. In fact his first job out of college was to take over support of VLSIextract (our circuit extractor), which I had written. But we are getting ahead.

    Michael was… Read More