Webinar: Verisium Debug for UVM Testbench

Webinar: Verisium Debug for UVM Testbench
by Admin on 09-25-2023 at 2:44 pm

Date: Wednesday, October 4, 2023

Time: 11:00am PT | 1:00pm CT | 2:00pm ET

Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug … Read More


Webinar: Basics of Low-Power Verification and Low-Power Simulation using Xcelium & Verisium Debug

Webinar: Basics of Low-Power Verification and Low-Power Simulation using Xcelium & Verisium Debug
by Admin on 08-31-2023 at 1:53 pm

Date and time: Thursday, September 7, 13:00-14:15

Organizer:

Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division

Cost: Free

Venue: Online (Zoom webinar)

*It is also possible to participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: Wednesday, … Read More


Webinar: Verisium Debug for UPF Low Power Design

Webinar: Verisium Debug for UPF Low Power Design
by Admin on 06-08-2023 at 9:50 pm

Date: Tuesday, June 20, 2023

Time: 11:00am PDT | 2:00pm EDT | 7:00pm CET

Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium… Read More


AI in Verification – A Cadence Perspective

AI in Verification – A Cadence Perspective
by Bernard Murphy on 04-04-2023 at 6:00 am

Opening slide min

AI is everywhere or so it seems, though often promoted with insufficient detail to understand methods. I now look for substance, not trade secrets but how exactly they using AI. Matt Graham (Product Engineering Group Director at Cadence) gave a good and substantive tutorial pitch at DVCon, with real examples of goal-centric optimization… Read More


Webinar: Shorten Your CDC Debug Cycle by 10X with ML-based RCA

Webinar: Shorten Your CDC Debug Cycle by 10X with ML-based RCA
by Admin on 03-16-2023 at 2:33 pm

Wednesday, April 5, 2023 | 10:00 – 11:00 a.m. Pacific

Over the last few decades System on Chip (SoC) design size has dramatically increased, and more complexity has been introduced to deliver the desired functionality. Growing design sizes lead to the introduction of several asynchronous clocks which can result in the

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Finally, A Serious Attack on Debug Productivity

Finally, A Serious Attack on Debug Productivity
by Bernard Murphy on 09-20-2022 at 6:00 am

Verisium min

Verification technologies have progressed in almost all domains over the years. We’re now substantially more productive in creating tests for block, SoC and hybrid software/hardware verification. These tests provide better coverage through randomization and formal modeling. And verification engines are faster – substantially… Read More


AI-Driven Verification: Saving Time with Verdi Regression Debug Automation

AI-Driven Verification: Saving Time with Verdi Regression Debug Automation
by Admin on 07-11-2022 at 9:25 pm

Synopsys Webinar | Wednesday, July 27, 2022 | 10:00 a.m. Pacific

Analyzing the thousands of failures from daily regression runs is a manual, tedious, and error-prone process. The process can significantly impact quality-of-results, time-to-results and cost-of-results. The Synopsys Verdi® Regression Debug Automation

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Getting to Faster Closure through AI/ML, DVCon Keynote

Getting to Faster Closure through AI/ML, DVCon Keynote
by Bernard Murphy on 03-10-2022 at 10:00 am

Manish min

Manish Pandey, VP R&D and Fellow at Synopsys, gave the keynote this year. His thesis is that given the relentless growth of system complexity, now amplified by multi-chiplet systems, we must move the verification efficiency needle significantly. In this world we need more than incremental advances in performance. We need… Read More


Improve your Debug Productivity

Improve your Debug Productivity
by Admin on 05-03-2021 at 2:46 pm

With today’s more complex designs, we tend to see a growing productivity gap between design and verification, so we need to maximize the reusability of your verification environment, improve the automation, raise the level of abstraction… but we need higher performance, context-aware debug supporting the complete logic verification

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Embedded Analytics Becoming Essential

Embedded Analytics Becoming Essential
by Tom Simon on 04-22-2021 at 6:00 am

Embedded Analytics

SoC integration offers huge benefits through reduced chip count in finished systems, higher performance, improved reliability, etc. A single die can contain billions of transistors, with multiple processors and countless subsystems all working together. The result of this has been rapid growth of semiconductor content … Read More