Improve your Debug Productivity

Improve your Debug Productivity
by Admin on 05-18-2021 at 12:00 am

With today’s more complex designs, we tend to see a growing productivity gap between design and verification, so we need to maximize the reusability of your verification environment, improve the automation, raise the level of abstraction… but we need higher performance, context-aware debug supporting the complete logic verification

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Embedded Analytics Becoming Essential

Embedded Analytics Becoming Essential
by Tom Simon on 04-22-2021 at 6:00 am

Embedded Analytics

SoC integration offers huge benefits through reduced chip count in finished systems, higher performance, improved reliability, etc. A single die can contain billions of transistors, with multiple processors and countless subsystems all working together. The result of this has been rapid growth of semiconductor content … Read More


Increase Your Debug Efficiency Using a Modern Debug Environment

Increase Your Debug Efficiency Using a Modern Debug Environment
by Admin on 06-03-2020 at 2:00 pm

Register For This Web Seminar

Online – Jun 3, 2020
14:00 – 15:00 Europe/Berlin

Overview

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines,

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What are you ready to mobilize for FPGA debug?

What are you ready to mobilize for FPGA debug?
by Frederic Leens on 12-04-2017 at 7:00 am

There are 3 common misconceptions about debugging FPGA with the real hardware:

[LIST=1]

  • Debugging happens because the engineers are incompetent.
  • FPGA debugging on hardware ‘wastes’ resources.
  • A single methodology should solve ALL the problems.
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    Optimizing Prototype Debug

    Optimizing Prototype Debug
    by Bernard Murphy on 11-09-2016 at 7:00 am

    In the spectrum of functional verification platforms – software-based simulation, emulation and FPGA-based prototyping – it is generally agreed that while speed shoots up by orders of magnitude (going left to right) ease of debug drops as performance rises and setup time increases rapidly, from close to nothing for simulation… Read More


    Getting out of DIY mode for virtual prototypes

    Getting out of DIY mode for virtual prototypes
    by Don Dingee on 09-26-2016 at 4:00 pm

    Virtual prototyping has, inexplicably, been largely a DIY thing so far. Tools and models have come from different sources with different approaches, and it has been up to the software development team to do the integration step and cobble together a toolchain and methodology that fits with their development effort.

    That integration… Read More


    A New Player in the Functional Verification Space

    A New Player in the Functional Verification Space
    by Bernard Murphy on 08-22-2016 at 7:00 am

    Israel has a strong pedigree in functional verification. Among others, Verisity (an early contributor to class-based testbench design and constrained random testing) started in Israel and RocketTick (hardware-based simulation acceleration), acquired more recently by Cadence, is based in Israel. So when I hear about an … Read More


    Learn How to Debug UVM Test Benches Faster – Upcoming Synopsys Webinar

    Learn How to Debug UVM Test Benches Faster – Upcoming Synopsys Webinar
    by Bernard Murphy on 07-14-2016 at 4:00 pm

    UVM for developing testbenches is a wonderful thing, as most verification engineers will attest. It provides abstraction capabilities, it encapsulates powerful operations, it simplifies and unifies constrained-random testing – it has really revolutionized the way we verify at the block and subsystem level.

    However great… Read More


    Bringing Formal Verification into Mainstream

    Bringing Formal Verification into Mainstream
    by Pawan Fangaria on 04-28-2016 at 7:00 am

    Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More


    Mentor at DVCon – Visualize This

    Mentor at DVCon – Visualize This
    by Bernard Murphy on 03-10-2016 at 12:00 pm

    Steve Bailey entertained us during lunch on Tuesday with a talk on debug and visualization in the Mentor platform. Steve is based in Colorado, so had to spend the first part of his talk gloating about their Super Bowl win, but I guess he deserves that.

    On a more technical note, he showed us a familiar survey they had completed with the… Read More