Date: Wednesday, October 4, 2023
Time: 11:00am PT | 1:00pm CT | 2:00pm ET
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug … Read More
Date and time: Thursday, September 7, 13:00-14:15
Organizer:
Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division
Cost: Free
Venue: Online (Zoom webinar)
*It is also possible to participate from a web browser.
We recommend using Google Chrome, Firefox, or Chromium Edge.
Registration deadline: Wednesday, … Read More
Date: Tuesday, June 20, 2023
Time: 11:00am PDT | 2:00pm EDT | 7:00pm CET
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium… Read More
AI is everywhere or so it seems, though often promoted with insufficient detail to understand methods. I now look for substance, not trade secrets but how exactly they using AI. Matt Graham (Product Engineering Group Director at Cadence) gave a good and substantive tutorial pitch at DVCon, with real examples of goal-centric optimization… Read More
Verification technologies have progressed in almost all domains over the years. We’re now substantially more productive in creating tests for block, SoC and hybrid software/hardware verification. These tests provide better coverage through randomization and formal modeling. And verification engines are faster – substantially… Read More
Manish Pandey, VP R&D and Fellow at Synopsys, gave the keynote this year. His thesis is that given the relentless growth of system complexity, now amplified by multi-chiplet systems, we must move the verification efficiency needle significantly. In this world we need more than incremental advances in performance. We need… Read More
SoC integration offers huge benefits through reduced chip count in finished systems, higher performance, improved reliability, etc. A single die can contain billions of transistors, with multiple processors and countless subsystems all working together. The result of this has been rapid growth of semiconductor content … Read More
