Israel has a strong pedigree in functional verification. Among others, Verisity (an early contributor to class-based testbench design and constrained random testing) started in Israel and RocketTick (hardware-based simulation acceleration), acquired more recently by Cadence, is based in Israel. So when I hear about an emerging Israel-based company in functional verification, I pay attention. Vtool is such a company, spun out of the Veriest FV consulting services company in 2014. I spoke recently with Hagai Arbel, the CEO.
Hagai’s focus is on simplifying and optimizing UVM testbench creation and on providing new/improved methods to debug. His company offers 3 tools: Machina, Vitalitas (not yet released) and Cogita. These are verification environment tools – they sit around whatever core simulator you happen to use.
Let’s start with Machina. It should come as no surprise to anyone that UVM, while it has done a great job by providing a standard foundation for testbenches, has also in a sense created a new career path, requiring a long apprenticeship to reach the lofty heights of UVM expert. That’s good for careers, not so much for getting designs signed off quickly. Worse yet, testbenches now contain 3-10 times as much code as the DUT, making the testbench a fertile breeding ground for many more bugs than you may find in the design. Building UVM testbenches isn’t just complicated, it’s very error-prone and debugging those testbenches can significantly amplify the verification workload.
The standard recipe for helping with this problem is libraries of predefined UVC components and graphical tools to build UVC components and protocol interfaces. Machina provides a nice implementation of these with on-the-fly linting and a drag and drop interface to build graphical flows, but this isn’t radically different from what the main simulation guys provide. What sets Machina apart, they tell me, is that their builder is completely interoperable between hand-crafted testbenches and the graphical variety. So you can start in text, improve it in the graphical interface, go back to text for some specialized changes from another team, go back into the graphical interface, … I have some familiarity from my Atrenta days with what works in graphical aids to RTL design. Interoperability makes a huge difference in usability and productivity because tasks that require text editing and tasks that benefit from the GUI don’t always nicely partition. Vtool said that one of their customers told them it took 2-3 hours to implement a UVC with Vtool, and without Vtool it would have typically taken them 2-3 days.
Vitalitas (not yet released) provides a visual method to build sequences in the form of flowcharts of scenarios; from this it will generate UVM code. This graph-based scenario method is becoming popular in the industry as a path to building more portable testbenches. I won’t go into more detail here since the product is pre-release but there is more info on the website.
Cogita is a novel debugger which you would very likely use as a complement to your standard debugger. It lets you write complex search patterns, for example to look for APB transactions and reads the simulation log files to produce graphical views based on those patterns. This can be extremely helpful in looking for suspicious behavior, something that’s not necessarily wrong but maybe unexpected. Particularly this helps you looks for unusual correlations between patterns that you expect to correlate in certain ways.
Hagai told me they are seeing adoption of the tool suite especially in companies that have not yet built up significant UVM infrastructure. There is particular interest in companies doing FPGA design for whom the big ASIC tool flows are still not so familiar. I would expect they may also see growth among UVM non-experts (aka most UVM users) around testbench generation. Vtool is distributed in the US by Consensia. You can learn more about Vtool HERE.