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Webinar: Top Five Challenges Preventing Design Closure!

Webinar: Top Five Challenges Preventing Design Closure!
by Daniel Nenni on 03-31-2017 at 4:00 pm

According to a recent engineering survey, completing IC designs on time and within specifications gets exponentially more challenging with each node. Why? Here are the top five reasons:


The thing I like about webinars is that they are free (I really like free) and you can register even if you can’t make the specific time/day then pull up the replay when you do have the time. The live version is much better of course because you get to interact with some very intelligent and experienced people. It is a form of networking that should be leveraged whenever possible for sure.

For example, with this webinar you will get to meet Bijan Dorostkar. Bijan came to Consensia from Qualcomm where he spent nine years in the Design Management EDA Infrastructure Team and yes, Qualcomm uses the software in question. So if you want to know how Qualcomm gets its chips out in a timely manner this is the webinar for you:

Join us for a Pinpoint Analytics Webinar

Thursday April 6, 2017 – 8.00am PDT / 11.00am EDT

  • Your designs in a 95% complete state for the last 30% of the design cycle time
  • You need to identify issues with your design immediately using real time metrics
  • You’d like to do more design experimentation but don’t have the time
  • You spend too much time preparing for design reviews instead of debugging

If you can agree with any of these statements, this webinar is for you!

This webinar, hosted by Consensia, a channel partner of Dassault Systemes, and moderated by Daniel Nenni of Semiwiki.com, will be of interest to anyone involved in ASIC/SOC or FPGA design. It will illustrate the benefits of using advanced analytics to overcome design challenges and address issues which delay time to design closure.

Using Pinpoint, a powerful analytics solution, you’ll see how its ‘Out Of The Box’ dashboards, reports and layout views help digital design teams achieve faster design closure by displaying real time design metrics and analytics for every design flow step, and for every part of the design from full chip to gate level, together on one dashboard.

You will learn why Pinpoint is used by leading SOC and FPGA design teams to collaborate across global design centers to keep designs ‘on track’ by immediately identifying and resolving potential issues in every aspect of their flow from synthesis to physical verification.

Register today to see how Pinpoint can help you get to faster design closure!

My interest in this webinar should be obvious, it is all about advanced analytics/big data and I am all about analytics/big data. I spend a disturbing amount of time looking at the advanced analytics/big data surrounding the semiconductor ecosystem to find out who is doing what, when, and where, in order to make the predictions I do both publicly and privately. It will be interesting to see similar techniques used for ASIC and FPGA design, absolutely.

I hope to see you there…


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