NoCs give architects flexibility in system-in RISC-V design

NoCs give architects flexibility in system-in RISC-V design
by Don Dingee on 11-16-2023 at 6:00 am

Power domains and crossings into NoC for system in RISC V design

RISC-V tends to generate excitement over the possibilities for the processor core, any custom instruction extensions, and its attached memory subsystem. Those are all necessary steps to obtaining system-level performance. But is that attention sufficient? Architects who have ventured into larger system-on-chip (SoC) … Read More


Upskill Your Smart Soldiers and Conquer the Chip War in Style!

Upskill Your Smart Soldiers and Conquer the Chip War in Style!
by Sivakumar PR on 07-21-2023 at 6:00 am

Maven Silicon Article Figure 1

My recent article, ‘Chip War without Soldiers’ explained the importance of upskilling and preparing the chip design workforce in this current scenario, and it also explained how it will lead to ‘Fabs without Chips’ if we don’t prioritize it. VLSI Engineers are the pillars of the semiconductor industry, and they can only transform… Read More


Defacto Celebrates 20th Anniversary @ DAC 2023!

Defacto Celebrates 20th Anniversary @ DAC 2023!
by Daniel Nenni on 07-05-2023 at 10:00 am

20ans signature clean

Defacto Technologies is a company that specializes in Electronic Design Automation (EDA) software and solutions. Defacto offers a range of EDA software solutions that help streamline and optimize various stages of the front-end design process. Their tools focus on chip design assembly and integration before logic synthesis

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Post-quantum cryptography steps on the field

Post-quantum cryptography steps on the field
by Don Dingee on 08-01-2022 at 6:00 am

PQSubSys post quantum cryptography IP

In cybersecurity circles, the elephant in the room is a quantum computer in the hands of nefarious actors. A day is coming, soon, when well-funded organizations will be able to rent time on, or maybe even build or buy a quantum machine. Then, if data is valuable enough, people will hunt for it. Two or three months of compute time on a … Read More


White Paper: Advanced SoC Debug with Multi-FPGA Prototyping

White Paper: Advanced SoC Debug with Multi-FPGA Prototyping
by Daniel Nenni on 04-19-2022 at 10:00 am

S2C EDA Prototyping White Paper 2022

S2C EDA recently released a whitepaper written by a good friend of mine Steve Walters. Steve and I have worked together many times throughout our careers and I consider him to be one of my trusted few, especially in regards to prototyping and emulation. Steve is also my co author on the book “Prototypical II The Practice of FPGA-Based… Read More


IoT’s Inconvenient Truth: IoT Security Is a Never-Ending Battle

IoT’s Inconvenient Truth: IoT Security Is a Never-Ending Battle
by Dana Neustadter on 06-01-2021 at 10:00 am

IoTs Inconvenient Truth IoT Security Is a Never Ending Battle

The continued innovation and widespread adoption of connected devices — the internet of things (IoT) — has resulted in a vast range of conveniences that improve our lives every day. At the same time, the ubiquity of IoT devices, which market watchers estimate to be in the tens of billions, also makes it more attractive to bad actors… Read More


Prototyping with the Latest and Greatest Xilinx FPGAs

Prototyping with the Latest and Greatest Xilinx FPGAs
by Daniel Nenni on 11-11-2020 at 6:00 am

Prototyping with the Latest and Greatest Xilinx FPGAs

I was reading the S2C press release announcing their new FPGA prototyping platform based on the Xilinx UltraScale+ VU19P FPGA, and how the new FPGA will accelerate billion gate FPGA prototyping, and I was struck by the stunning implications of this announcement.  Not that billion gate SoC designs can now be prototyped with FPGAs,… Read More


Embedded Systems Development Flow

Embedded Systems Development Flow
by Daniel Nenni on 11-09-2020 at 6:00 am

Webinar SoC 1

Earlier this year. as part of my coverage of the virtual Design Automation Conference (DAC), I interviewed Agnisys CEO and founder Anupam Bakshi. He talked about the new products they introduced at the show and filled me in on the history of the company and his own background. Recently, Anupam presented the webinar “System Development… Read More


Why IP Designers Don’t Like Surprises!

Why IP Designers Don’t Like Surprises!
by Daniel Nenni on 03-13-2020 at 6:00 am

IPDelta SemiWiki

If it’s your job to get a SoC design through synthesis, timing/power closure and final verification, the last thing you need are surprises in new versions of the IP blocks that are integrated into the design. If your IP supplier sends a new version, the best possible scenario is that this is only a small incremental change from… Read More


WEBINAR: Lightspeed Data Sync – Design Workspace Problems Solved!

WEBINAR: Lightspeed Data Sync – Design Workspace Problems Solved!
by Daniel Nenni on 09-02-2019 at 10:00 am

With every process node and every SOC design, engineering and IT teams are experiencing an unprecedented data explosion. User workspaces routinely exceed 10’s of GB and sometimes even 100’s of GB. Regression runs, characterization runs, design and debug of workspaces, building verification environments – all of these… Read More