Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVision Pro can do with mixed-signal design debug. Sujit works at EDA Direct, a company started in 1997 providing EDA tools from Mentor, Cliosoft and Concept Engineering, along with training and services.
The StarVision Pro tool comes from Concept Engineering, an EDA company from Germany that has been in business for three decades now. I first heard about Concept Engineering about 18 years ago, because the EDA company that I worked at had a need to visualize SPICE netlists as schematics to better understand circuit simulation results from a Fast SPICE tool. It’s been rewarding to see the growth of features as StarVision Pro has expanded its scope to cover so many input file formats:
The wow moment is when you read in a file format and then quickly visualize an automatic schematic, neatly laid out with inputs on the left and outputs on the right showing you all of the interconnect, cell instances and hierarchy. Circuit designers, logic designers and even DFT engineers can each benefit from quickly seeing how an SoC is assembled. For logic verification you can even see the logic state on each net in a design as a function of time.
During a live demo on a laptop running Linux I saw Sujit read in a digital design, and this works even if your design is incomplete, missing IP or has syntax errors. Just look at how neat the auto-generated schematic appears:
Useful debugging features include:
- Click any net and dynamically expand a cone of logic
- Cross-probe between schematic and RTL source code
- Search for nets by filtering a name
- Trace an internal net to an IO pin
In the screenshot above we’ve loaded in logic simulation results from a VCD file, then moved to a specific time point in the simulation run, and finally visualize the logic state on our nets. This kind of visual debug really speeds up the functional verification process to find and fix bugs.
The next design file to be read in was from a parasitic extraction tool as a SPEF file, so we can quickly see the RC values that make up a net. This screenshot shows how you can click on the schematic and cross-probe into the source file:
An engineer can then find which nets are the heaviest loaded, and Sujit ran a pre-built script that allowed him to filter and remove all capacitors below a threshold value.
A SPICE netlist was loaded, and we viewed the MOS transistors, along with some parasitic capacitors:
Next, we wanted to know what had changed in a SPICE netlist over time, so a DIFF script quickly highlight where the differences were located by showing that net n6 was modified:
StarVision Pro comes with some 100 scripts, so I got the idea that they had automated most debugging tasks for me, saving me time from having to write my own scripts. Of course, you can always just view the Tcl source code for the scripts, and create new derivatives and combinations to make your debugging happen faster.
On YouTube there’s a channel for EDA Direct, and they’ve recorded over a dozen intro videos on specific StarVision Pro topics, and each video is brief at under 2 minutes of viewing time:
- Quick Start Video #1 – RTL Design
- Quick Start Video #2 – Analog Circuit Design
- Quick Start Video #3 – Basic Design Navigation
- Quick Start Video #4 – Design Navigation using Incremental Schematic
Designing, verifying and re-using mixed-signal chips and IP blocks can be a tedious and error-prone task, especially since most of the file formats are textual, which makes them difficult to understand as part of a larger or hierarchical design. Using an automatic visualization tool like StarVision Pro is sure to save you hours and days of engineering effort, because now you can see the structure of your IC design, along with simulation values in an intuitive schematic format. Circuit designers, logic designers, DFT engineers and verification engineers can all benefit by adding a tool like this to their methodology.