Mixed-Signal Debugging Gets a Boost

Mixed-Signal Debugging Gets a Boost
by Daniel Payne on 03-30-2020 at 6:00 am

starvision pro

Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVisionRead More


Challenges in IP Qualification with Rising Physical Data

Challenges in IP Qualification with Rising Physical Data
by Pawan Fangaria on 12-17-2015 at 7:00 am

With every new technology node, there are newer physical effects that need to be taken into account. And every new physical effect brings with itself several new formats to model them. Often a format is also associated with several of its derivatives, sometimes an standard reincarnation of a proprietary format further evolved… Read More


Build Low Power IoT Design with Foundation IP at 40nm

Build Low Power IoT Design with Foundation IP at 40nm
by Pawan Fangaria on 07-28-2015 at 12:00 pm

In a power hungry world of semiconductor devices, multiple ways are being devised to budget power from system to transistor level. The success of IoT (Internet of Things) Edge devices specifically depend on lowest power, lowest area, optimal performance, and lowest cost. These devices need to be highly energy efficient for sustained… Read More


An Universe of Formats for IP Validation

An Universe of Formats for IP Validation
by Pawan Fangaria on 06-19-2015 at 4:30 pm

Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the… Read More