Electromigration and IR Drop Analysis has a New Entrant

Electromigration and IR Drop Analysis has a New Entrant
by Daniel Payne on 09-28-2021 at 9:00 am

mPower capacity

My first IR drop analysis was back in the early 1980s at Intel, where I had to manually model the parasitics of the VDD and VSS interconnect for all of the IO cells that our team was designing in a graphics chip, then I ran that netlist in a SPICE simulator using transient analysis, measuring the bounce in VSS and droop in VDD levels as all… Read More


AMS IC Designers need Full Tool Flows

AMS IC Designers need Full Tool Flows
by Daniel Payne on 08-31-2021 at 10:00 am

AMS tool flow min

Digital IC design gets a lot of attention, because all of our modern devices primarily use digital logic, but in reality whenever you have a sensor like a camera,  accelerometer, gyroscope or any radio like Bluetooth, WiFi or NFC, then you’re really in the realm of analog, and that’s where mixed-signal  IC design comes… Read More


EDA in the Cloud – Now More Than Ever

EDA in the Cloud – Now More Than Ever
by Kalar Rajendiran on 07-27-2021 at 10:00 am

Screen Shot 2021 07 14 at 4.32.16 PM

A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More


RealTime Digital DRC Can Save Time Close to Tapeout

RealTime Digital DRC Can Save Time Close to Tapeout
by Tom Simon on 06-07-2021 at 6:00 am

RealTime DRC

Over the years DRC tools have done an admirable job of keeping pace with the huge growth of IC design size. Yet, DRC runs for sign off on the full design using foundry rule decks take many hours to complete. These long run times are acceptable for final sign off, but there are many situations where DRC results are needed quickly when small… Read More


Calibre DFM Adds Bidirectional DEF Integration

Calibre DFM Adds Bidirectional DEF Integration
by Tom Simon on 01-26-2021 at 6:00 am

Siemens EDA DFM flow

GDS and LEF/DEF each came about to support data exchange in different types of design flows, custom layout and place & route respectively. GDS (or stream format) was first created in the late 1970s to support the first generation of custom IC layout tools, such as Calma’s GDSII system. Of course, the GDS format has been updated… Read More


Configuration Environment is Make-or-Break for IC Verification

Configuration Environment is Make-or-Break for IC Verification
by Tom Simon on 12-10-2020 at 10:00 am

IC Verification Environment

All semiconductor design work today rests on the three-legged stool of Foundries, EDA Tools and Designers. Close collaboration between the three make possible the successful completion of ever more complex designs, especially those at advanced nodes. Perhaps one of the most critical intersections of all three is during physical… Read More


How to Use Calibre for Physical Verification

How to Use Calibre for Physical Verification
by Admin on 07-08-2020 at 10:00 am

Register For This Web Seminar

Online – Jul 8, 2020
10:00 – 11:00 Asia/Singapore

Overview

Physical Verification Overview

  • Calibre Physical Verification General Introduction
  • Basic Calibre Process Flow
  • Calibre Hierarchical Processing
  • How to Run Calibre DRC
  • DRC Extension: eqDRC, Fast XOR and Antenna Checks
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Mixed-Signal Debugging Gets a Boost

Mixed-Signal Debugging Gets a Boost
by Daniel Payne on 03-30-2020 at 6:00 am

starvision pro

Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVisionRead More


Saving Time in Physical Verification by Reusing Metadata

Saving Time in Physical Verification by Reusing Metadata
by Daniel Payne on 01-08-2020 at 10:00 am

voltage propagation cross reference data min

Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:

  • Physical validation
  • Circuit validation
  • Reliability verification

This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More


Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required… Read More