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Calibre IC Manufacturing papers at SPIE 2023

Calibre IC Manufacturing papers at SPIE 2023
by Daniel Nenni on 03-07-2023 at 6:00 am

SPIE 2023 San Jose

The Siemens Calibre group was very busy last week at SPIE. Calling Calibre industry leading really is an understatement. Calibre is one of the reasons Moore’s Law has continued to this day. This tool is legendary. You can get more information on the Calibre landing page including product information, resource guide, blogs and much more:

Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

SPIE Advanced Lithography + Patterning

SPIE is the international society for optics and photonics. We bring engineers, scientists, students, and business professionals together to advance light-based science and technology.

In case you missed SPIE or you missed some of the Calibre papers here they are. If you would like us to dig deeper on any one of them let me know, fascinating stuff, absolutely:

Join Calibre IC Manufacturing at SPIE Advanced Lithography 2023, Feb 26 – March 3, 2023, at the San Jose Convention Center. Siemens will be presenting 16 papers. (All presentations listed in Pacific Time.)

27 February 2023

27 February 2023 • 10:50 AM – 11:10 AM
Structured assist features in inverse lithography
Paper 12495-2

27 February 2023 • 4:20 PM – 4:40 PM
Resolution enhancement techniques @0.55 NA EUV applied for 6th generation of 10nm DRAM Joint paper of IMEC and Siemens EDA
Paper 12495-9

28 February 2023

28 February 2023 • 1:40 PM – 2:10 PM
Extending design technology co-optimization from technology launch to HVM (Keynote Presentation)
Paper 12495-14

28 February 2023 • 3:40 PM – 4:10 PM
EUV Full-chip curvilinear mask options for logic via and metal patterning (Invited Paper)
Paper 12495-18

1 March 2023

1 March 2023 • 10:30 AM – 10:50 AM
Stochastic aware EUV OPC on random logic via Joint paper of IMEC and Siemens EDA
Paper 12494-26

1 March 2023 • 10:50 AM – 11:10 AM
A ML based OPC model pattern down-selection method with mask and wafer contours
Paper 12499-17

1 March 2023 • 1:20 PM – 1:40 PM
IC layouts patterns topological profiling using directional geometrical kernels Joint paper of Ain Shams University and Siemens EDA
Paper 12495-29

1 March 2023 • 5:30 PM – 7:00 PM
CPU time prediction using machine learning for post-tapeout flow runs (PTOF)
Paper 12495-64

1 March 2023 • 5:30 PM – 7:00 PM
Design-aware virtual metrology and process recipe recommendation Joint paper of GlobalFoundries and Siemens EDA
Paper 12495-75

1 March 2023 • 5:30 PM – 7:00 PM
Impact of mask rule constraints on ideal SRAF placement
Paper 12494-54

1 March 2023 • 5:30 PM – 7:00 PM
EUV SRAFs printing modeling and verification in 2D hole array Joint paper of IMEC and Siemens EDA
Paper 12494-61

1 March 2023 • 5:30 PM – 7:00 PM
Design rule manual and DRC code qualification flows empowered by high coverage synthetic layouts generation Joint paper of SAMSUNG Electronics and Siemens EDA
Paper 12495-72

1 March 2023 • 5:30 PM – 7:00 PM
Application of Gaussian Random Field EUV stochastic model to quantification of stochastic variability of EUV vias Joint paper of IMEC and Siemens EDA
Paper 12494-67

1 March 2023 • 5:30 PM – 7:00 PM
AI-guided reliability diagnosis for 5,7nm automotive process Joint paper of SAMSUNG Electronics and Siemens EDA
Paper 12496-142

1 March 2023 • 5:30 PM – 7:00 PM
Hybrid deep learning OPC framework with generative adversarial network Joint paper of Institute of Microelectronics, Beijing Superstring Academy of Memory Technology, and Siemens EDA
Paper 12495-69

2 March 2023

2 March 2023 • 8:00 AM – 8:30 AM
Novel approach to solving systematic pattern yield limiters with volume scan diagnosis (Invited Paper) Joint paper of PDF Solutions and Siemens EDA
Paper 12495-39

2 March 2023 • 11:00 AM – 11:20 AM
Unsupervised ML classification driven process model coverage check Joint paper of SAMSUNG Electronics and Siemens EDA
Paper 12495-44

Also Read:

The State of FPGA Functional Verification

Interconnect Choices for 2.5D and 3D IC Designs

The State of IC and ASIC Functional Verification

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