Stop TDDB from getting through peanut butter

Stop TDDB from getting through peanut butter
by Don Dingee on 01-24-2014 at 6:00 pm

Image RemovedThere are a few dozen causes of semiconductor failure. Most can be lumped into one of three categories: material defects, process or workmanship issues, or environmental or operational overstress. Even when all those causes are carefully mitigated, one factor is limiting reliability more as geometries shrink… Read More


TSMC ♥ Mentor (Calibre PERC)

TSMC ♥ Mentor (Calibre PERC)
by Daniel Nenni on 10-29-2013 at 8:00 am

As semiconductors become more integrated into our lives reliability is becoming a critical issue. As IP consumes more of our die, IP reliability is becoming a critical issue. As we pack more transistors into a chip, reliability is becoming a critical issue. As we move from 28nm to 20nm to 16nm, reliability is becoming a critical … Read More


How to Simplify Complexities in Power Verification?

How to Simplify Complexities in Power Verification?
by Pawan Fangaria on 10-17-2013 at 11:00 am

With multiple functionalities added into a single chip, be it a SoC or an ASIC, maintaining low power consumption has become critical for any design. Various techniques at the technology as well as design level are employed to accomplish the low power target. These include thinner oxides in transistors, different sections of … Read More


A Programmable Electrical Rule Checker

A Programmable Electrical Rule Checker
by Daniel Payne on 04-29-2013 at 11:21 pm

IC designers involved with physical design are familiar with acronyms like DRC (Design Rule Check), LVS (Layout Versus Schematic) and DFM (Design For Manufacturing), but how would you go about checking for compliance with ESD (Electro Static Discharge) rules? You may be able to kludge something together with your DRC tool and… Read More


ESD – Key issue for IC reliability, how to prevent?

ESD – Key issue for IC reliability, how to prevent?
by Pawan Fangaria on 04-23-2013 at 8:30 pm

It’s a common electrical rule that when large amount of charge gets accumulated, it tries to break any of its surrounding isolation. Although it wouldn’t have been prominent in 1980s or 90s, protection for ICs from such damaging effects is a must, specifically in large mixed-signal designs of today, working at different voltages… Read More


IC Reliability and Prevention During Design with EDA Tools

IC Reliability and Prevention During Design with EDA Tools
by Daniel Payne on 04-27-2012 at 5:04 pm

IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here’ s a list of reliability issues to keep you awake at night:… Read More


Transistor-Level Electrical Rule Checking

Transistor-Level Electrical Rule Checking
by Daniel Payne on 04-20-2011 at 11:19 am

Introduction
Circuit designers work at the transistor level and strive to get the ultimate in performance, layout density or low power by creating crafty circuit topologies in both schematics and layout. Along with this quest comes the daunting task of verifying that all of your rules and best practices about reliability have… Read More


Intel Sandy Bridge Fiasco and EDA

Intel Sandy Bridge Fiasco and EDA
by Daniel Nenni on 02-27-2011 at 6:49 am

I purchased two Toyotas last year and both have since been recalled. Why has Toyota spent $1B+ on recalls in recent years? Same reason why it will cost Intel $700M (which does not include reputation damage) to recall Sandy Bridge chip sets, because someone did not do their job! The WHAT has been discussed, lets talk about HOW it happened.… Read More