As semiconductors become more integrated into our lives reliability is becoming a critical issue. As IP consumes more of our die, IP reliability is becoming a critical issue. As we pack more transistors into a chip, reliability is becoming a critical issue. As we move from 28nm to 20nm to 16nm, reliability is becoming a critical issue. The last time one of my “always on” mobile devices became unreliable I tossed it out my car window on Highway 101. So yes, semiconductor reliability is an issue.
PERC is now integrated into the TSMC 9000 IP program so the hundreds, if not thousands, of IP that flow through TSMC can be verified using focused reliability checks for 28nm, 20nm, and 16nm process nodes. SoC designers can then run PERC at the chip level to revalidate the IP after integration. Given the shrinking design cycles and re-spin costs this is a no brainer. The ROI of a thorough and trusted (repeatable) verification environment is compelling.
To investigate further there are several articles about Calibre PERC on SemiWiki:
- How to Simplify Complexities in Power Verification
- A Programmable Electrical Rule Checker
- Static Low-Power Verification in Mixed-Signal SoC Designs
- Robust Reliability Verification: Beyond Traditional Tools and Techniques
- ESD – Key issue for IC reliability, how to prevent?
- Automating Complex Circuit Checking Tasks
- High Frequency Analysis of IC Layouts
Mentor also has a nice Calibre PERC page HERE with white papers, webinars, and videos including this one: