Electrical Reliability Verification – Now At FullChip

Electrical Reliability Verification – Now At FullChip
by Alex Tan on 04-25-2018 at 12:00 pm

Image RemovedAdvanced process technology offers both device and interconnect scaling for increased design density and higher performance while invoking also significant implementation complexities. Aside from the performance, power and area (PPA) aspects, designer is getting entrenched with the need of tackling more… Read More


Robust Reliability Verification – A Critical Addition To Baseline Checks

Robust Reliability Verification – A Critical Addition To Baseline Checks
by Alex Tan on 03-01-2018 at 12:00 pm

Design process retargeting is aImage Removedcommon recurrence based on scaling orBOM(Bill-Of-Material) cost improvement needs. This occursnot only with the availability of foundry process refresh to a more advanced node,but also to any new derivative process node tailored towards matching design complexity, power profileRead More


Is there anything in VLSI layout other than “pushing polygons”? (5)

Is there anything in VLSI layout other than “pushing polygons”? (5)
by Dan Clein on 01-11-2018 at 12:00 pm

Image RemovedBeing new in Ottawa and trying to get some momentum towards automation in full custom layout I was telling industry people that I am interested to work with everybody to move this agenda forward. My Director of Engineering at that time, Peter Gillingham, took me to visit Carleton University in Ottawa. One of his professor… Read More


High Calibre Development Keeps Mentor on Top of the Game

High Calibre Development Keeps Mentor on Top of the Game
by Tom Simon on 12-07-2017 at 12:00 pm

One might be tempted to think that technology driven gains in computer performance might be enough to keep up with the needs of design and verification tools. We know that design complexity is increasing at a rate predicted by Moore’s Law. We also know that the performance of the computers used during IC development benefit from … Read More


Why Open and Supported Interfaces Matter

Why Open and Supported Interfaces Matter
by Mitch Heins on 08-29-2017 at 12:00 pm

Back in the early 1980’s during the nascent years of electronic design automation (EDA), I worked at Texas Instruments supporting what would become their merchant ASIC business. Back then, life was a bit different. The challenge we faced was to make our ASIC library available on as many EDA flows as we could to give as many users as… Read More


Mentor & Phoenix Software Shed Light on Integrated Photonics Design Rule Checking

Mentor & Phoenix Software Shed Light on Integrated Photonics Design Rule Checking
by Mitch Heins on 07-10-2017 at 12:00 pm

Just prior to the opening of the 54[SUP]th[/SUP] Design Automation Conference, Mentor, a Siemens company, and PhoeniX Software issued a press release announcing a new integration between their tools to help designers of photonic ICs (PICs) to close the loop for manufacturing sign-off verification. This is a significant piece… Read More


Dear Cadence: Calibre Didn’t Run Any Dracula Decks

Dear Cadence: Calibre Didn’t Run Any Dracula Decks
by Mitch Heins on 05-04-2017 at 2:00 pm

After reading the Cadence blog post –Dracula, Vampire, Assura, PVS: A Brief History” – Dr. Andrew Moore has written the below article where he helps readers get a sense as to what “the year of hell” was like, from one of the key individuals who lived it. Andrew also addresses and corrects some of the “urban legendsRead More


Calibre Can Calculate Chip Yields Correlated to Compromised SRAM Cells

Calibre Can Calculate Chip Yields Correlated to Compromised SRAM Cells
by Tom Simon on 04-11-2017 at 12:00 pm

It seems like I have written a lot about SRAM lately. Let’s face it SRAM is important – it often represents large percentages of the area on SOC’s. As such, SRAM yield plays a major role in determining overall chip yields. SRAM is vulnerable to defect related failures, which unlike variation effects are not Gaussian in nature. Fabrication… Read More


Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration

Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration
by Mitch Heins on 01-20-2017 at 12:00 pm

Image RemovedI caught up with John Ferguson of Mentor Graphics this week to learn more about a recent announcement that TSMC has extended its collaboration with Mentor in the area of Fan-Out Wafer Level Processing (FOWLP).

In March of last year Mentor and TSMC announced that they were collaborating on a design and verification … Read More


Mentor’s Battle of the Photonic Bulge

Mentor’s Battle of the Photonic Bulge
by Mitch Heins on 12-07-2016 at 4:00 pm

Image RemovedA few weeks back I wrote an article mentioning that Mentor Graphics has been quietly working on solutions for photonic integrated circuits (PICs) for some time now, while one of their competitors has recently established a photonics beachhead. One of the most common challenges for PIC designs is their curvilinear… Read More