A Hardware IDE for VS Code Fans

A Hardware IDE for VS Code Fans
by Daniel Nenni on 11-22-2022 at 10:00 am

VS Code Remote SSH Article Diagram

A few times a year, I check in with AMIQ EDA co-founder Cristian Amitroaie to see what’s new with their company and the integrated development environment (IDE) market for hardware design and verification. Usually he suggests a topic for us to discuss, but this time I specifically wanted to learn more about the version of their Design… Read More


Bespoke Silicon Requires Bespoke EDA

Bespoke Silicon Requires Bespoke EDA
by Michiel Ligthart on 10-26-2022 at 10:00 am

Bespoke EDA

When I first heard the term ‘bespoke silicon,’ I had to get my dictionary out. Well versed in the silicon domain, I did not know what bespoke meant. It turns out to be a rather old-fashioned term for tailor made and seems to be very much British English. The word dates from 1583 and is the past participle of bespeak, according… Read More


Sigasi September Productivity Hacks Workshop

Sigasi September Productivity Hacks Workshop
by Admin on 08-15-2022 at 3:17 pm

Thursday, September 15, 2022, at 11am CEST/10am WEST/2:30pm IST/5am EST/2am PST

Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs. Visuals of your code update instantly and are cross-linked to your code to allow graphical

Read More

Sigasi September Productivity Hacks Workshop

Sigasi September Productivity Hacks Workshop
by Admin on 08-15-2022 at 3:15 pm

Tuesday, September 13, 2022, at 8pm CEST/7pm WEST/2pm EST/11am PST/11:30pm IST

Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs. Visuals of your code update instantly and are cross-linked to your code to allow graphical

Read More

Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM

Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
by Admin on 06-08-2022 at 2:50 pm

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

Part 2: Faster than “Lite” Verification Component Development with OSVVM (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, June 9, 2022

11:00 AM – 12:00 PM (PDT)… Read More


LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)
by Admin on 05-18-2022 at 4:35 pm

Part 1: OSVVM – Leading Edge Verification for the VHDL Community (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, May 26, 2022

11:00 AM – 12:00 PM (PDT)

Abstract:

OSVVM is an advanced verification methodology that defines a VHDL verification framework,

Read More

Verific Sharpening the Saw

Verific Sharpening the Saw
by Bernard Murphy on 02-11-2022 at 6:00 am

Sharpening the saw min

Verific is an unusual company. They are completely dominant in what they do – providing parsers for Verilog/SV, VHDL and UPF. Yet they have no ambition to expand beyond that goal. Instead, per Michiel Ligthart (President and COO), they continue to “sharpen the saw”. This is an expression I learned in sales training, habit #7 from… Read More


COO Interview: Michiel Ligthart of Verific

COO Interview: Michiel Ligthart of Verific
by Daniel Nenni on 05-14-2021 at 6:00 am

Michiel Ligthart wpcf 120x170

Today, Semiwiki profiles Verific Design Automation, perhaps the most popular company at DAC (when it’s an in-person event) because of its giveaway –– a 10”stuffed giraffe for anyone who walks up to its booth and listens to its story.

But, Verific is also a popular EDA company for more reasons than its tradeshow  giveaway.… Read More


Why I made the world’s first on-demand formal verification course

Why I made the world’s first on-demand formal verification course
by Ashish Darbari on 04-18-2021 at 6:00 am

formal use model 2


Verification Challenge
As chip design complexity continues to grow astronomically with hardware accelerators running riot with the traditional hardware comprising CPUs, GPUs, networking and video and vision hardware, concurrency, control and coherency will dominate the landscape of verification complexity for safe … Read More


The Polyglot World of Hardware Design and Verification

The Polyglot World of Hardware Design and Verification
by Daniel Nenni on 07-23-2020 at 10:00 am

SemiWiki article

It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More