Introduction to Visualizer for the VHDL Users

Introduction to Visualizer for the VHDL Users
by Admin on 06-30-2020 at 8:00 am

2 thumbnail

Register For This Web Seminar

Online – Jun 30, 2020
8:00 AM – 9:00 AM US/Pacific

Overview

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines,

Read More

Introduction to Visualizer for the VHDL Users

Introduction to Visualizer for the VHDL Users
by Admin on 06-30-2020 at 8:00 am

4 thumbnail

Register For This Web Seminar

Online – Jun 30, 2020
8:00 AM – 9:00 AM US/Pacific

Overview

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines,

Read More

Mixed-Signal Debugging Gets a Boost

Mixed-Signal Debugging Gets a Boost
by Daniel Payne on 03-30-2020 at 6:00 am

starvision pro

Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVisionRead More


Webinar: Designing Complex SoCs and Dealing with Multiple File Formats

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats
by Daniel Payne on 08-12-2019 at 10:00 am

StarVision Pro

In SoC design it’s all about managing complexity through modeling, and the models that make up IC designs come in a wide range of file formats like:

  • Transistor-level , SPICE
  • Interconnect parasitics, SPEF
  • Gate and RTL, Verilog, VHDL

Even with standard file formats, designers still have to traverse the hierarchy to find out… Read More


Foundational Excellence in a Laid-Back Style

Foundational Excellence in a Laid-Back Style
by Bernard Murphy on 04-24-2019 at 7:00 am

I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL. When you hear a line like that, you assume a heavy dose of marketing spin, but here it really is fact. I don’t know of… Read More


Design Automation and the Engineering Workstation

Design Automation and the Engineering Workstation
by Daniel Nenni on 09-28-2018 at 7:00 am

This is the seventeenth in the series of “20 Questions with Wally Rhines”

Several common aspects have existed for what is now the modern Electronic Design Automation (EDA) industry. When I joined TI in 1972, the company was very proud of its design automation capability as a competitive differentiator. Much of the… Read More


Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More


CEO Interview: Cristian Amitroaie of AMIQ EDA

CEO Interview: Cristian Amitroaie of AMIQ EDA
by Bernard Murphy on 07-05-2018 at 7:00 am

AMIQ EDA has caught my attention over the last few months. My first impression was that this was just another small IDE company trying to compete with established and bundled IDEs from the big 3, a seemingly insurmountable barrier. This view was challenged by an impressive list of testimonials, not just from the little guys but also… Read More


A Picture is worth a 1,000 words

A Picture is worth a 1,000 words
by Daniel Payne on 12-28-2017 at 7:00 am

Semiconductor IP re-use is a huge part of the productivity gains in SoC designs, so instead of starting from a clean slate most chip engineers are re-using cells, blocks, modules and even sub-systems from previous designs in order to meet their schedule and stay competitive in the market place. But what happens when you intend to… Read More


Getting More Productive Coding with SystemVerilog

Getting More Productive Coding with SystemVerilog
by Daniel Payne on 08-31-2017 at 12:00 pm

HDL languages are a matter of engineering personal preference and often corporate policy dictates which language you should be using on your next SoC design. In the early days we used our favorite text-based editor like Vi or Emacs, my choice was Vi. The problem with these text-based editors of course is that they really don’t… Read More