The Polyglot World of Hardware Design and Verification

The Polyglot World of Hardware Design and Verification
by Daniel Nenni on 07-23-2020 at 10:00 am
Categories: AMIQ EDA, EDA
1 Comment

It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More

Introduction to Visualizer for the VHDL Users

Introduction to Visualizer for the VHDL Users
by Admin on 06-30-2020 at 8:00 am

Register For This Web Seminar

Online – Jun 30, 2020
8:00 AM – 9:00 AM US/Pacific

Overview

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines,

Introduction to Visualizer for the VHDL Users

Introduction to Visualizer for the VHDL Users
by Admin on 06-30-2020 at 8:00 am

Register For This Web Seminar

Online – Jun 30, 2020
8:00 AM – 9:00 AM US/Pacific

Overview

March 30, 2020July 28, 2020

Mixed-Signal Debugging Gets a Boost

Mixed-Signal Debugging Gets a Boost
by Daniel Payne on 03-30-2020 at 6:00 am
Categories: Concept Engineering, EDA

Having the right tool for the job at hand is always a joy, and when your IC project involves RTL code, gates, transistors and even parasitic interconnect, then you need some EDA tool help for debugging and finding out why your design behaves the way it is. An FAE named Sujit Roy did a conference call with me last week to show what StarVision… Read More

August 12, 2019September 16, 2019

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats
by Daniel Payne on 08-12-2019 at 10:00 am
Categories: Concept Engineering, EDA, Events

In SoC design it’s all about managing complexity through modeling, and the models that make up IC designs come in a wide range of file formats like:

Transistor-level , SPICE
Interconnect parasitics, SPEF
Gate and RTL, Verilog, VHDL

Even with standard file formats, designers still have to traverse the hierarchy to find out… Read More

April 24, 2019May 6, 2020

Foundational Excellence in a Laid-Back Style

Foundational Excellence in a Laid-Back Style
by Bernard Murphy on 04-24-2019 at 7:00 am
Categories: EDA

I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL. When you hear a line like that, you assume a heavy dose of marketing spin, but here it really is fact. I don’t know of… Read More

September 28, 2018

Design Automation and the Engineering Workstation

Design Automation and the Engineering Workstation
by Daniel Nenni on 09-28-2018 at 7:00 am
Categories: Wally Rhines
2 Comments

This is the seventeenth in the series of “20 Questions with Wally Rhines”

Several common aspects have existed for what is now the modern Electronic Design Automation (EDA) industry. When I joined TI in 1972, the company was very proud of its design automation capability as a competitive differentiator. Much of the… Read More

September 26, 2018

Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm
Categories: EDA, Fractal Technologies, IP, TSMC

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More

July 5, 2018June 29, 2020

CEO Interview: Cristian Amitroaie of AMIQ EDA

CEO Interview: Cristian Amitroaie of AMIQ EDA
by Bernard Murphy on 07-05-2018 at 7:00 am
Categories: AMIQ EDA, CEO Interviews, EDA

AMIQ EDA has caught my attention over the last few months. My first impression was that this was just another small IDE company trying to compete with established and bundled IDEs from the big 3, a seemingly insurmountable barrier. This view was challenged by an impressive list of testimonials, not just from the little guys but also… Read More

December 28, 2017

A Picture is worth a 1,000 words

A Picture is worth a 1,000 words
by Daniel Payne on 12-28-2017 at 7:00 am
Categories: EDA, Sigasi
3 Comments

Semiconductor IP re-use is a huge part of the productivity gains in SoC designs, so instead of starting from a clean slate most chip engineers are re-using cells, blocks, modules and even sub-systems from previous designs in order to meet their schedule and stay competitive in the market place. But what happens when you intend to… Read More

Array ( [0] => tribe-events-list-widget-5 [1] => search-2 [2] => media_image-8 [3] => better_recent_comments-2 [4] => media_image-12 ) WP_Term Object ( [term_id] => 2580 [name] => vhdl [slug] => vhdl [term_group] => 0 [term_taxonomy_id] => 2580 [taxonomy] => post_tag [description] => [parent] => 0 [count] => 36 [filter] => raw [is_post] => )

Tribe__Events__List_Widget Instance: 5Array ( [title] => Upcoming Events [limit] => 5 [no_upcoming_events] => [featured_events_only] => [jsonld_enable] => 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [display_widget_mobile] => 1 )

Array ( [title] => Upcoming Events [limit] => 5 [no_upcoming_events] => [featured_events_only] => [jsonld_enable] => 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [display_widget_mobile] => 1 )

WP_Widget_Search Instance: 2Array ( [display_widget_title] => on [title] => Search Semiwiki [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [display_widget_mobile] => 1 [rw_opt_exclude] => Array ( ) )

Array ( [display_widget_title] => on [title] => Search Semiwiki [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [display_widget_mobile] => 1 [rw_opt_exclude] => Array ( ) )

WP_Widget_Media_Image Instance: 8Array ( [display_widget_title] => on [attachment_id] => 291446 [url] => https://semiwiki.com/wp-content/uploads/2020/10/YieldHUB-SemiWiki-Webinar-300x300.jpg [title] => [size] => medium [width] => 2560 [height] => 2560 [caption] => [alt] => YieldHUB SemiWiki Webinar [link_type] => custom [link_url] => https://attendee.gotowebinar.com/register/6445215525925579788?source=SemiWiki.com [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => [image_title] => [display_widget_mobile] => [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) )

Barn2\Plugin\Better_Recent_Comments\Widget Instance: 2Array ( [title] => Recent Article Comments [number] => 8 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Array ( [title] => Recent Article Comments [number] => 8 [avatar] => [date] => 1 [comment] => 1 [link] => 1 [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

WP_Widget_Media_Image Instance: 12Array ( [display_widget_title] => on [size] => full [width] => 400 [height] => 400 [caption] => [alt] => WIKI White Paper HDL Simulation Acceleration for Microchip FPGA Designs [link_type] => custom [link_url] => https://bit.ly/31zAnwy [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => [image_title] => [attachment_id] => 292410 [url] => https://semiwiki.com/wp-content/uploads/2020/10/WIKI_White-Paper_HDL-Simulation-Acceleration-for-Microchip-FPGA-Designs.jpg [title] => [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [display_widget_mobile] => )

Array ( [0] => rpwe_widget-9 [1] => gtranslate-3 [2] => media_image-9 [3] => xfrp_widget-2 [4] => media_image-13 ) WP_Term Object ( [term_id] => 2580 [name] => vhdl [slug] => vhdl [term_group] => 0 [term_taxonomy_id] => 2580 [taxonomy] => post_tag [description] => [parent] => 0 [count] => 36 [filter] => raw [is_post] => )

Recent_Posts_Widget_Extended Instance: 9Array ( [title] => Trending Now [title_url] => [ignore_sticky] => 1 [exclude_current] => 1 [limit] => 5 [offset] => 10 [order] => DESC [orderby] => date [post_type] => Array ( [0] => post ) [post_status] => publish [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 10 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => Read More [comment_count] => [thumb] => [thumb_height] => 55 [thumb_width] => 55 [thumb_default] => [thumb_align] => rpwe-alignleft [styles_default] => 1 [cssID] => [css_class] => [css] => .rpwe-block ul{ list-style: none !important; margin-left: 0 !important; padding-left: 0 !important; } .rpwe-block li{ border-bottom: 1px solid #eee; margin-bottom: 10px; padding-bottom: 10px; list-style-type: none; } .rpwe-block a{ display: inline !important; text-decoration: none; } .rpwe-block h3{ background: none !important; clear: none; margin-bottom: 0 !important; margin-top: 0 !important; font-weight: 400; font-size: 12px !important; line-height: 1.5em; } .rpwe-thumb{ border: 1px solid #eee !important; box-shadow: none !important; margin: 2px 10px 2px 0; padding: 3px !important; } .rpwe-summary{ font-size: 12px; } .rpwe-time{ color: #bbb; font-size: 11px; } .rpwe-comment{ color: #bbb; font-size: 11px; padding-left: 5px; } .rpwe-alignleft{ display: inline; float: left; } .rpwe-alignright{ display: inline; float: right; } .rpwe-aligncenter{ display: block; margin-left: auto; margin-right: auto; } .rpwe-clearfix:before, .rpwe-clearfix:after{ content: ""; display: table !important; } .rpwe-clearfix:after{ clear: both; } .rpwe-clearfix{ zoom: 1; } [before] => [after] => [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [display_widget_mobile] => )

GTranslateWidget Instance: 3Array ( [title] => Google Translate [rw_opt] => Array ( [pageid_281769] => 1 [pageid_281772] => 1 [widget_select] => 1 ) [display_widget_mobile] => )

WP_Widget_Media_Image Instance: 9Array ( [display_widget_title] => on [size] => full [width] => 400 [height] => 400 [caption] => [alt] => Semiwiki 400x400 [link_type] => custom [link_url] => https://www.agnisys.com/events/webinar-on-system-development-using-agnisys/ [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => [image_title] => [attachment_id] => 292418 [url] => https://semiwiki.com/wp-content/uploads/2020/10/Semiwiki_400x400.jpg [title] => [display_widget_mobile] => [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) )

XF2_Latest_Posts_Widget Instance: 2Array ( [title] => Recent Forum Threads [title_url] => [ignore_sticky] => 0 [exclude_current] => 0 [limit] => 10 [offset] => 0 [order] => [orderby] => ID [post_type] => Array ( [0] => post ) [post_status] => [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 0 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => [comment_count] => [thumb] => [thumb_height] => 0 [thumb_width] => 0 [thumb_default] => [thumb_align] => [styles_default] => [cssID] => [css_class] => [css] => [before] => [after] => [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [sluglist] => ["jobs-dashboard"] [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

Array ( [title] => Recent Forum Threads [title_url] => [ignore_sticky] => 0 [exclude_current] => 0 [limit] => 10 [offset] => 0 [order] => [orderby] => ID [post_type] => Array ( [0] => post ) [post_status] => [cat] => Array ( ) [tag] => Array ( ) [taxonomy] => [excerpt] => [length] => 0 [date] => [date_relative] => [date_modified] => [readmore] => [readmore_text] => [comment_count] => [thumb] => [thumb_height] => 0 [thumb_width] => 0 [thumb_default] => [thumb_align] => [styles_default] => [cssID] => [css_class] => [css] => [before] => [after] => [display_widget_mobile] => 1 [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) [sluglist] => ["jobs-dashboard"] [rw_opt_exclude] => Array ( [pageid_274493] => 1 ) )

WP_Widget_Media_Image Instance: 13Array ( [display_widget_title] => on [size] => full [width] => 400 [height] => 400 [caption] => [alt] => Webinar 2 [link_type] => custom [link_url] => https://attendee.gotowebinar.com/register/9157755792430558219?source=SemiWiki [image_classes] => [link_classes] => [link_rel] => [link_target_blank] => [image_title] => [attachment_id] => 292409 [url] => https://semiwiki.com/wp-content/uploads/2020/10/Webinar-2.jpg [title] => [display_widget_mobile] => [rw_opt] => Array ( [widget_select] => 1 [pageid_281769] => 1 [pageid_281772] => 1 ) )