During SNUG I took the opportunity to chat to Choon-Hoe Yeoh of Lattice Semiconductor about how they use Concept Engineering’s Starvision Pro product. He is the senior director of EDA tools and methodologies there.
Lattice Semiconductor is a manufacturer of low-power, small-footprint, low-cost programmable logic devices. Earlier this month it closed an acquisition of Silicon Image, a leading provider of multimedia connectivity solutions and services for mobile, consumer electronics and PC markets based in Sunnyvale, CA.
One of their products is the world’s smallest, lowest power, most integrated, most flexible mobile FPGA. With up to 4,000 LUTs and key IP for IR, barcode, voice, USB-C, user ID, LEDs, pedometer, and more. Perfect for the IoT and mobile markets!
StarVision Pro provides engineers with the ability to quickly and easily understand and debug mixed-mode designs and to integrate IP building blocks into their complex SoCs and ICs. Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages and netlist formats.
Choon is responsible for design enablement at Lattice, including tools, methods, flows, PDKs, license queuing and so on. Lattice has been using Starvision Pro for a couple of years. They use it primarily for better visualization of chip level design. These are difficult to work with in a “classical” schematic tool since the designs are a mixture of actual gate-level and transistor-level schematics along with Verilog. Starvision Pro helps to improve productivity at chip level design debugging as it gives the designers system-level visibility which is important since FPGA design is a mixture of full-custom and RTL with a number of different variants of the flow.
Choon expects to expand the use in the future, and is looking at various ways that different products and flows could benefit.
Here in a single table is a concise summary of the features of Starvision Pro.
| style=”text-align: center” | Features
| style=”text-align: center” | Benefits
| Ultra fast HDL reader and graphics on the fly
| Graphical representations make it easier to understand, debug, change and optimize Verilog, VHDL and SystemVerilog code
| Schematics from SPICE netlists
| Schematics provide easier and faster debugging for complex circuits. Supported dialects include SPICE, HSPICE, Spectre, Calibre, CDL, Eldo and PSPICE.
| 32/64-bit database
| Higher performance and increased capacity, for very large designs
| Powerful GUI
| Multiple views, including tree, schematic, waveform and source file plus drag and drop between different views for increased circuit understanding
| Cone Window
| Incremental schematic navigation for easy design exploration
| Tcl UserWare API
| Allows interfacing with tool flow and definition of electrical rule checks
| Circuit fragment save
| Circuit netlists can be saved as SPICE files or Verilog files for future reuse as IP, or for partial simulation
| Automatic clock tree and clock domain extraction and visualization
| Faster detection and resolution of clock domain problems
| Full support for mixed language and mixed-signal designs
| Designers can easily develop and debug today’s most complex heterogeneous designs (SystemVerilog, Verilog, VHDL, SPICE, HSPICE,…)
| Parasitic analysis features
| Allows visualization and analysis of parasitic networks (DSPF, RSPF, SPEF) and provides capabilities to create SPICE netlists for critical circuit fragment simulation.