ASYNC 2022 Summer School: Gate-level design

ASYNC 2022 Summer School: Gate-level design
by Admin on 06-13-2022 at 12:00 am

The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design.  The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design.  Participants will learn how to design asynchronous circuits at the behavioral level, … Read More


Webinar: Getting to Accurate Power Estimates Earlier and Faster

Webinar: Getting to Accurate Power Estimates Earlier and Faster
by Bernard Murphy on 05-24-2017 at 7:00 am

Power has become a very important metric in modern designs – for mobile and IoT devices which must live on a battery charge for days or years, for datacenters where power costs can be as significant as capital costs, and for increasingly unavoidable regulatory reasons. But accurate power estimation on a design must start from an … Read More


Starvision Pro: Lattice Semiconductor’s Experience

Starvision Pro: Lattice Semiconductor’s Experience
by Paul McLellan on 04-09-2015 at 7:00 am

During SNUG I took the opportunity to chat to Choon-Hoe Yeoh of Lattice Semiconductor about how they use Concept Engineering’s Starvision Pro product. He is the senior director of EDA tools and methodologies there.

Lattice Semiconductor is a manufacturer of low-power, small-footprint, low-cost programmable logic devices.… Read More