WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 422
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 422
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
    [is_post] => 1
)

Ensuring Safety Distinctive Design & Verification

Ensuring Safety Distinctive Design & Verification
by Pawan Fangaria on 12-21-2014 at 12:00 pm

In today’s world where every device functions intelligently, it automatically becomes active on any kind of stimulus. The problem with such intelligence is that it can function unfavorably on any kind of bad stimulus. As the devices are complex enough in the form of SoCs (which at advanced process nodes are more susceptible to external exposure such as radiation, static charge etc.) encompassing rich set of multiple functions, it’s essential to condition those to function favourably even in the event of any unexpected stimulus. While the functional safety of these devices are critical in automotive, aerospace, and healthcare applications, other applications such as industrial, home, consumer etc. are not isolated considering financial loss. So, how to make the SoCs immune to unexpected, unplanned or unintended (may be by human itself) stimuli and condition them to work safely in any environment at the chip or system level?

At the design level, SoCs need to be made fault-tolerant by introducing alternative paths to process at the expense of added redundancy and at the same time special checkers need to be introduced to monitor the system and trigger error response and recovery when needed.

To verify the system and ensure tool confidence level (TCL), the verification must include safety verification along with functional verification at all levels of abstractions from system to components. The functional tests must be replayed after injecting faults into the system to ensure correct working of alternative paths on correct data and of checkers on erroneous data monitoring and recovery.

Cadencehas beautifully extended its Incisive functional verification platform for functional safety verification. The platform has demonstrated well in complying with automotive safety standards and has been used in production by several automotive IC suppliers.

The Incisive verification platform seamlessly augments functional verification plan with Safety Verification Plan that meets complete functional safety assessment, requirements and TCL. The metric-driven verification (read Effective Verification Coverage through UVM & MDV to know more about metric-driven verification) is used to effectively monitor sets of metadata through complete verification flow including functional and safety requirements. The functional safety assessment is done by simulating system behavior (that includes IP, SoC and complete system) through Incisive Functional Safety Simulator (that includes permanent as well as transient fault simulation) under various error conditions. The fault models include manufacturing-time stuck-at-0 and stuck-at-1 faults, as well as single event upset faults and transient faults that can occur while the ICs are functioning in the system.

Cadence’s functional safety solution is very efficient in providing complete tracing of requirements, safety verification and TCL that conforms to automotive ISO 26262 standard. The automated solution from requirements to verification and TCL reduces ISO 26262 certification effort by ~50%.

The Incisive Functional Safety Simulator accelerates safety verification by seamlessly reusing functional and mixed-signal verification environment that provides 10X runtime performance compared to traditional Verifault-XL engine used in functional safety simulation. The existing SystemVerilog, UVM or e functional verification environments can be reused as usual. The faults are injected during simulation of DUT and can propagate through SystemC, analog transistor or behavioral models, and assertions.

The Incisive vManager automatically generates a safety verification regression from the fault dictionary created by the simulator. It can then track millions of detected, potentially detected, and undetected faults introduced into simulation to verify the safety in a design.

Both the Incisive Functional Safety Simulator and vManager are part of Cadence System Development Suite. They address dependability and reliability of the system which has become a critical criterion (together with PPA) today in the face of nanometer process nodes.

Cadence continues to expand its functional safety solution portfolio by including more hardware, software and IP components in different application areas. A more detailed view on the automotive functional safety solution is available in a whitepaperat Cadence website, written by Philippe Roche of STMicroelectronicsand Adam Sherer of Cadence.

More Articles by PawanFangaria…..


0 Replies to “Ensuring Safety Distinctive Design & Verification”

You must register or log in to view/post comments.