Tag: gdsii

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Honey I Shrunk the EDA TAM

Honey I Shrunk the EDA TAM
by Daniel Nenni on 10-19-2018 at 7:00 am
Categories: Wally Rhines

The “20 Questions with Wally Rhines” series continues

Throughout the history of the EDA industry, pricing models have caused discontinuities in the way the industry operates. For a variety of competitive reasons, individual companies have developed ways to change the pricing model in an attempt to secure competitive… Read More

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Is there anything in VLSI layout other than “pushing polygons”? (3)

Is there anything in VLSI layout other than “pushing polygons”? (3)
by Dan Clein on 11-13-2017 at 12:00 pm
Categories: EDA
3 Comments

In late 1986 the Layout Project Leader of DSP96000 got married and left for a 6 months’ vacation so I inherited the biggest chip MSIL had in stock. Floorplanning such size chip was a challenge from day one. Even the 68030 SUN workstation was too slow. I started to ask around and going to demos for any other possible tool that can help me… Read More

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Is there anything in VLSI layout other than pushing polygons? (2)

Is there anything in VLSI layout other than pushing polygons? (2)
by Dan Clein on 10-04-2017 at 12:00 pm
Categories: Cadence, Concept Engineering, General, Mentor, a Siemens Business, Synopsys

One of the important changes that happen between 1984 and 1988 is the hardware platforms development. Calma evolved, mainframe S140 with 2 combined monitors per terminal in S280 with 2 individual monitors per terminal. This meant that from noisy and darker rooms we move to more quiet and lighted rooms. We doubled the speed and the… Read More

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Why Open and Supported Interfaces Matter

Why Open and Supported Interfaces Matter
by Mitch Heins on 08-29-2017 at 12:00 pm
Categories: EDA, Mentor, a Siemens Business

Back in the early 1980’s during the nascent years of electronic design automation (EDA), I worked at Texas Instruments supporting what would become their merchant ASIC business. Back then, life was a bit different. The challenge we faced was to make our ASIC library available on as many EDA flows as we could to give as many users as… Read More

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Business Models: EDA Is Software But It Used To Be Sold As Hardware

Business Models: EDA Is Software But It Used To Be Sold As Hardware
by Paul McLellan on 09-03-2015 at 7:00 am
Categories: EDA, General

Business models are really important. Just ask any internet startup company that has lots of eyeballs and is trying to work out how to monetize them. It is a lot easier to get people to use something for free, much harder to get people to pay for something especially when they don’t value it much. Different companies that look… Read More

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eSilicon Creates One-Click Access to MPW and GDSII Quoting Portals

eSilicon Creates One-Click Access to MPW and GDSII Quoting Portals
by Paul McLellan on 10-23-2014 at 7:00 am
Categories: eSilicon, Semiconductor Services

I have written before about eSilicon taking their internal quoting tool and making it user accessible. This first started just for MPW shuttles for half-a-dozen foundries, and then was extended to cover production runs at TSMC. And it is getting heavily used; eSilicon have had 315 people register to use it from 43 different countries… Read More

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Xilinx & Apache Team up for FPGA Reliability at 20nm

Xilinx & Apache Team up for FPGA Reliability at 20nm
by Pawan Fangaria on 03-17-2014 at 12:00 am
Categories: ANSYS, Inc., EDA, FPGA, Xilinx

In this age of SoCs with hundreds of IPs from different sources integrated together and working at high operating frequencies, FPGA designers are hard pressed keeping up the chip reliability from issues arising out of excessive static & dynamic IR drop, power & ground noise, electro migration and so on. While the IPs are… Read More

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Patterns looking inside, not just between, logic cells

Patterns looking inside, not just between, logic cells
by Don Dingee on 12-27-2013 at 5:00 pm
Categories: Uncategorized

Traditional logic testing relies on blasting pattern after pattern at the inputs, trying to exercise combinations to shake faults out of logic and hopefully have them manifested at an observable pin, be it a test point or a final output stage. It’s a remarkably inefficient process with a lot of randomness and luck involved.

Getting… Read More

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Robust Design <- Robust Flow <- Robust Tools

Robust Design <- Robust Flow <- Robust Tools
by Pawan Fangaria on 08-10-2013 at 6:00 pm
Categories: ANSYS, Inc., EDA

I could have written the sequence of the title in reverse order, but no, design is the one which initiates the need of a particular flow and the flow needs support of EDA tools to satisfy that need. It’s okay if the design is small; some manual procedures and workarounds/scripts may be able to perform certain jobs. However, as the design… Read More

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A Brief History of EDA

A Brief History of EDA
by Daniel Nenni on 08-05-2012 at 6:00 pm
Categories: EDA

Electronic Design Automation, or more affectionately known as EDA, is a relatively young $5B industry with a very colorful upbringing, one that I have experienced firsthand, I’m very grateful for, and is an honor to write about. Today EDA employs an estimated 27,000 people! There is a nice EDA Wikipedia page which can be found here… Read More