Debugging SoCs at the RTL, Gate and SPICE Netlist Levels

Debugging SoCs at the RTL, Gate and SPICE Netlist Levels
by Daniel Payne on 10-02-2019 at 10:00 am

Debugging an IC is never much fun because of all the file formats used, the levels of hierarchy and just the sheer design size, so when an EDA tool comes around that allows me to get my debugging done quicker, then I take notice and give it a look. I was already familiar with debugging SPICE netlists using a tool called SPICEVision Pro,… Read More


#56DAC Update – What’s New at Concept Engineering

#56DAC Update – What’s New at Concept Engineering
by Daniel Payne on 07-02-2019 at 10:00 am

I first connected with Gerhard Angst of Concept Engineering over 15 years ago, because I was using their SpiceVision PRO tool to visual SPICE netlists received from customer designs to be debugged in a FastSPICE circuit simulator. The ability to visualize a transistor-level netlist was simply essential to quickly understanding… Read More


Making Things Visible for 25 Years

Making Things Visible for 25 Years
by Paul McLellan on 06-03-2015 at 7:00 am

Image RemovedThis year is most notably the 50th anniversary of Moore’s Law. It is also the 25th anniversary of Concept Engineering. They were founded in 1990 in Freiburg Germany. They started by providing automatic schematic generation from netlist. They sold primarily to other EDA companies and to internal development… Read More