With the increase in SoC designs’ sizes and complexities, the verification continuum has grown larger to an extent that the strategies for design convergence need to be applied from the very beginning of the design flow. Often designers are stuck with never ending iterations between RTL, gate and transistor levels at different stages of designs. In this light, full-chip analysis and verification completion for a large SoC may look like a distant dream. A significant number of iterations can be reduced by identifying and fixing bugs at the source, i.e. RTL.
One of the most effective ways to fix issues in the RTL is by running lint checks on the RTL code. But imagine the RTL code for a design with several hundred millions of gates; not only can the tool’s capacity and performance become prohibitive, but a huge number of violations can also become a problem to manage. So, what are the alternatives? Well, if we could use the link checks in a smarter way to cover the complete design in a reasonable time and effort, it could be a great alternative to make the design robust at RTL, for better convergence throughout the downstream design flow.
For complete analysis coverage, a flat design investigation is required which necessitates longer runtime and higher memory consumption. Also, block level waivers are required to defer violations for verified sub-blocks when run at the top level without sufficient or consistent constraints. It could be difficult and time consuming to resolve inconsistencies between the block and chip level lint rules.
A flat design analysis can also be carried out with IP or bocks used as black boxes, thus focusing only on chip level modules and glue logic. This approach can improve analysis runtime and reduce memory consumption and violation management. However, a major drawback in this approach is reduced analysis coverage and poor QoR. In this approach inter-block issues and several other issues such as improper use of clock and set/reset signals generated by an IP module remain undetected and uncovered.
Atrentahas come up with a novel approach that can provide the complete analysis coverage for an SoC with shorter runtime and lower memory consumption, and without the need of any waiver at the block level. They use smart or “Abstract Models” for IP blocks, a concept pioneered by Atrenta for full-chip analysis. How does the methodology with abstract models work? Let’s see an example –
In the above pictures there are abstract model views with a couple of typical input and output ports. An abstract model contains important information about the block’s interfaces such as its port types, their directions and the connected signals with them. This information is utilized in inter-block lint checks such as combinational loop fanning across multiple blocks, un-driven input terminal and so on. The abstract model also allows constant propagation that helps in detecting structural issues. The comprehensiveness of interface level information in the abstract models ensures the completeness of analysis coverage at the SoC level.
The “Abstract Model” based SoC lint analysis is done hierarchically in two steps –
In the first step, the block level constraints and assumptions are verified within the context of the SoC. This step ensures that the abstract models are in sync with the SoC analysis environment and requirements. Any inconsistencies and mismatches between block and chip level analysis are identified at this stage. In the second step, the final SoC analysis is done by using these verified abstract views for lower level blocks or IPs. No waiver is required at the SoC level. Since the lower level blocks are fully verified, the violations occur only at the chip level and can be easily managed.
Atrenta’s customers have verified many SoCs with this approach. The larger SoCs of the order of 200 to 350 million gates show an improvement of ~10x in runtime and reduction of ~5x in memory consumption with this hierarchical approach compared to the flat analysis approach. The hierarchical approach also shows better inter-block coverage compared to the IP black-box approach. At the same time, the violations are meaningful and easily manageable.
By using this lint methodology effectively at the RTL level, designers can quickly identify and remove potential issues related to design initialization, bus integrity, unreachable or unknown states, underflow or overflow of FIFOs, and so on to signoff the RTL for synthesis and implementation. The lint-clean RTL makes way for faster convergence of the SoC through downstream implementation and verification flow.
Atrenta is unveiling this new lint methodology for SoC signoff at the 52[SUP]nd[/SUP] DAC. Visit their booth #1732 to learn more.
Pawan Kumar Fangaria
Founder & President at www.fangarias.com