RAL, Lint and VHDL-2018

RAL, Lint and VHDL-2018
by Alex Tan on 06-11-2018 at 12:00 pm

Image RemovedFunctional verification is a very effort intensive and heuristic process which aims at confirming that system functionalities are meeting the given specifications. While pushing cycle-time improvement on the back-end part of this process is closely tied to the compute-box selection (CPU speed, memory capacity,… Read More


Aldec Rounds Out ALINT-PRO Checker

Aldec Rounds Out ALINT-PRO Checker
by Bernard Murphy on 02-16-2017 at 7:00 am

If there’s anyone out there who still doesn’t accept the importance of static RTL verification in the arsenal of functional verification methods, I haven’t met any recently. That wasn’t the case in my early days in this field. Back then I grew used to hearing “I don’t make mistakes in my RTL”, “I’ll catch that in simulation”, “My editor… Read More


A Robust Lint Methodology Ensures Faster Design Closure

A Robust Lint Methodology Ensures Faster Design Closure
by Pawan Fangaria on 06-03-2015 at 4:00 am

With the increase in SoC designs’ sizes and complexities, the verification continuum has grown larger to an extent that the strategies for design convergence need to be applied from the very beginning of the design flow. Often designers are stuck with never ending iterations between RTL, gate and transistor levels at different… Read More


Finding Logic Issues Early that Impact Physical Implementation

Finding Logic Issues Early that Impact Physical Implementation
by Daniel Payne on 10-16-2014 at 7:00 am

Complex SoC project teams typically use a divide and conquer approach where specialized engineers work in separate domains, like front-end or back-end. The five major engineering tasks for IC design can be described as: RTL design, synthesis, floor planning, place and route, then finally design analysis.

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What… Read More


Aldec Can Ensure Smooth System Integration

Aldec Can Ensure Smooth System Integration
by Luke Miller on 06-17-2014 at 9:00 pm

Tools, tools, tools. Designs are rapidly changing, JESD204b, Hybrid Memory cube and all other Gigabit serialization schemes are here to stay. RIP DDR. This means board level simulations with respect to firmware (FPGA) are going to be more challenging than ever. Why? you ask, especially if the board layout is simpler? True, but… Read More


You may want to check that known-good RTL

You may want to check that known-good RTL
by Don Dingee on 01-23-2013 at 1:00 pm

In his blog Coding Horror, Jeff Atwood wrote: “Software developers tend to be software addicts who think their job is to write code. But it’s not. Their job is to solve problems.” Whether the tool is HTML, C, or RTL, the reality is we are now borrowing or buying more software IP than ever, and integrating it into more complex designs,… Read More